Improved Accuracy Area Efficient Hybrid CMOS/GaN DC-DC Buck Converterfor High Step-Down Ratio Applications

abstract: Point of Load (POL) DC-DC converters are increasingly used in space applications, data centres, electric vehicles, portable computers and devices and medical electronics. Heavy computing and processing capabilities of the modern devices have ushered the use of higher battery supply voltage to increase power storage. The need to address this consumer experience driven requirement has propelled the evolution of the next generation of small form-factor power converters which can operate with higher step down ratios while supplying heavy continuous load currents without sacrificing efficiency. Constant On-Time (COT) converter topology is capable of achieving stable operation at high conversion ratio with minimum off-chip components and small silicon area. This work proposes a Constant On-Time buck dc-dc converter for a wide dynamic input range and load currents from 100mA to 10A. Accuracy of this ripple based converter is improved by a unique voltage positioning technique which modulates the reference voltage to lower the average ripple profile close to the nominal output. Adaptive On-time block features a transient enhancement scheme to assist in faster voltage droop recovery when the output voltage dips below a defined threshold. UtilizingGallium Nitride (GaN) power switches enable the proposed converter to achieve very high efficiency while using smaller size inductor-capacitor (LC) power-stage. Use of novel Superjunction devices with higher drain-source blocking voltage simplifies the complex driver design and enables faster frequency of operation. It allows 1.8VComplementary Metal-Oxide Semiconductor (CMOS) devices to effectively drive GaNpower FETs which require 5V gate signal swing. The presented controller circuit uses internal ripple generation which reduces reliance on output cap equivalent series resistance (ESR) for loop stability and facilitates ripples reduction at the output. The ripple generation network is designed to provide ai optimally stable performance while maintaining load regulation and line regulation accuracy withing specified margin. The chip with ts external Power FET package is proposed to be integrated on a printed circuit board for testing. The designed power converter is expected to operate under 200 MRad of a total ionising dose of radiation enabling it to function within large hadron collider at CERN and space satellite and probe missions.Dissertation/ThesisMasters Thesis Electrical Engineering 201

A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier

Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed-loop power control and operates under supply voltages from 2.9 V to 5.5 V in a standard micro-lead-frame package. It shows no oscillations, degradation, or failures for over 2000 hours of operation with a supply of 6 V at 135° under a VSWR of 15:1 at all phase angles and has also been tested for more than 2 million device-hours (with ongoing reliability monitoring) without a single failure under nominal operation conditions. It produces up to +35 dBm of RF power with power-added efficiency of 51%

Reliability analysis of foil substrate based integration of silicon chips

Flexible electronics has attracted significant attention in the recent past due to the booming wearables market in addition to the ever-increasing interest for faster, thinner and foldable mobile phones. Ultra-thin bare silicon ICs fabricated by thinning down standard ICs to thickness below 50 μm are flexible and therefore they can be integrated on or in polymer foils to create flexible hybrid electronic (FHE) components that could be used to replace rigid standard surface mount device (SMD) components. The fabricated FHE components referred as chip foil packages (CFPs) in this work are ideal candidates for FHE system integration owing to their ability to deliver high performance at low power consumption while being mechanically flexible. However, very limited information is available in the literature regarding the reliability of CFPs under static and dynamic bending. The lack of such vital information is a major obstacle impeding their commercialization. With the aim of addressing this issue, this thesis investigates the static and dynamic bending reliability of CFPs. In this scope, the static bending reliability of CFPs has been investigated in this thesis using flexural bending tests by measuring their fracture strength. Then, Finite Element Method (FEM) simulations have been implemented to calculate the fracture stress of ultra-thin flexible silicon chips where analytical formulas may not be applied. After calculating the fracture stress from FEM simulations, the enhancement in robustness of ultra-thin chips (UTCs) against external load has also been proved and quantified with further experimental investigations. Besides, FEM simulations have also been used to analyse the effect of Young’s Modulus of embedding materials on the robustness of the embedded UTCs. Furthermore, embedding the UTCs in polymer layers has also been experimentally proven to be an effective solution to reduce the influence of thinning and dicing induced damages on the robustness of the embedded UTCs. Traditional interconnection techniques such as wire bonding may not be implemented to interconnect ultra-thin silicon ICs owing to the high mechanical forces involved in the processes that would crack the chips. Therefore, two novel interconnection methods namely (i) flip-chip bonding with Anisotropic Conductive Adhesive (ACA) and (ii) face-up direct metal interconnection have been implemented in this thesis to interconnect ultra-thin silicon ICs to the corresponding interposer patterns on foil substrates. The CFP samples thus fabricated were then used for the dynamic bending reliability investigations. A custom-built test equipment was developed to facilitate the dynamic bending reliability investigations of CFPs. Experimental investigations revealed that the failure of CFPs under dynamic bending was caused mainly by the cracking of the redistribution layer (RDL) interconnecting the chip and the foil. Furthermore, it has also been shown that the CFPs are more vulnerable to repeated compressive bending than to repeated tensile bending. Then, the influence of dimensional factors such as the thickness of the chip as well as the RDL on the dynamic bending reliability of CFPs have also been studied. Upon identifying the plausible cause behind the cracking of the RDL leading to the failure of the CFPs, two methods to improve the dynamic bending reliability of the RDL have been suggested and demonstrated with experimental investigations. The experimental investigations presented in this thesis adds some essential information to the state-of-the-art concerning the static and the dynamic bending reliability of UTCs integrated in polymer foils that are not yet available in the literature and aids to establish in-depth knowledge of mechanical reliability of the components required for manufacturing future FHE systems. The strategies devised to enhance the robustness of UTCs and CFPs could serve as guidelines for fabricating reliable FHE components and systems

SiC MOSFET and GaN FET in high voltage switching applications

For several decades, silicon-based semiconductor devices, such as Si MOSFETs have been the main choice for switching applications. However, their level of performance is approaching its maximum potential, and further development becomes increasingly challenging. As a result, semiconductor manufacturers and the electronics industry are exploring new technologies to meet current requirements. One promising option is the use of WBG (Wide Band Gap) devices, such as GaN FETs and SiC MOSFETs, which have gained attention due to their superior performance characteristics. Compared to traditional Si transistors, WBG devices can withstand higher voltages and tem-peratures, are faster, can be packed in smaller sizes, and are more efficient. This study aims to serve as a guide for designers seeking information on the technology and usage of WBG transistors, particularly in high voltage switching applications. The study in-cludes an examination of the structures of SiC MOSFETs and GaN FETs, as well as their most important electrical characteristics. Additionally, the efficiency of an LCC converter was measured to compare the performance of various FET types, with a specific interest in the use of WBG devices in soft switching applications. Scientific articles, application notes, and datasheets were investigated to provide a thorough understanding of the theory behind SiC MOSFETs and GaN FETs. According to resources, the primary SiC MOSFET and GaN FET technologies suitable for high voltage switching are planar SiC MOSFET, trench SiC MOSFET, p-GaN FET and GaN/Si cascode transistor. These devices are currently available with breakdown voltages of 1700 V (planar SiC MOSFET), 2000 V (trench SiC MOSFET), 650 V (p-GaN FET) and 900 V (GaN/Si cascode transistor). The efficiency of an LCC converter with a maximum output power of 40 W was measured using 1500 V Si MOSFET, 1700 V planar SiC MOSFET, 1700 V trench SiC MOSFET, and 900 V GaN/Si cascode transistor. A constant load of 1 A was used, and the input voltage was incre-mentally increased from 300 V to 900 V in 100 V steps. According to results, using planar and trench SiC MOSFETs, LCC converter had the highest efficiency, reaching up to 89,6 % while Si MOSFET exhibited slightly lower efficiency, which was 87,7 % at its best. GaN/Si cascode tran-sistors showed comparable efficiency to SiC MOSFETs at lower input voltages but fell signifi-cantly behind as the voltage increased, having eventually much worse efficiency than Si MOSFET.Useiden vuosikymmenien ajan pii-pohjaiset puolijohteet, kuten pii MOSFETit, ovat olleet pääasiallinen teknologia katkojasovelluksissa. Niiden suorituskyky lähestyy kuitenkin ylärajaa, ja niiden kehittäminen käy yhä vaikeammaksi. Tämän vuoksi puolijohdevalmistajat ja elektroniikkateollisuus etsivät uusia teknologioita täyttää nykyiset vaatimukset. Yksi lupaava teknologia ovat laajan energiavyön puolijohteet, kuten galliumnitridi FETit ja piikarbidi MOSFETit. Viime vuosina ne ovat herättäneet paljon huomiota niiden ylivoimaisten ominaisuuksien vuoksi. Verrattuna perinteisiin pii MOSFETeihin, laajan energiavyön transistorit kestävät suurempia jännitteitä ja lämpötiloja, ovat nopeampia ja ne voidaan pakata pienempään kokoon. Lisäksi ne ovat tehokkaampia. Tämä diplomityö pyrkii toimimaan oppaana elektroniikkasuunnittelijoille, jotka etsivät tietoa laajan energiavyön transistoreista ja niiden käytöstä erityisesti suurjännitekatkojasovelluksissa.Työssä tarkastellaan piikarbidi MOSFETien ja galliumnitridi FETien rakenteita sekä niiden tärkeimpiä sähköisiä ominaisuuksia. Lisäksi mitattiin kelaan ja kahteen kondensaattoriin perustuvan LCC resonanssiteholähteen hyötysuhde eri FET-tyypeillä, koska haluttiin saada tietoa laajan energiavyön transistorien käytöstä pehmeässä jännitteen katkonnassa. Tiedon keräämiseksi tutkittiin tieteellisiä artikkeleita, sovellusohjeita ja datalehtiä. Lähdeaineiston perusteella pääasialliset piikarbidi MOSFETien ja galliumnitridi FETien teknologiat suurjännitesovellusten alueella ovat planaarinen piikarbidi MOSFET, erityiseen kaivanto teknologiaan (trench) perustuva piikarbidi MOSFET, p-tyypin galliumnitridi FET ja galliumnitridi/pii kaskadi transistori. Tällä hetkellä näitä teknologioita on kaupallisesti saatavilla enimmillään 1700 V (planaarinen piikarbidi MOSFET), 2000 V (kaivanto piikarbidi MOSFET), 650 V (p-tyypin galliumnitridi FET) ja 900 V (galliumnitridi/pii kaskadi transistori) jännitteillä. Nimellisteholtaan 40 W LCC resonanssi teholähteen hyötysuhde mitattiin 1500 V pii MOSFETeilla, 1700 V planaarisilla piikarbidi MOSFETeilla, 1700 V kaivanto piikarbidi MOSFETeilla ja 900 V gallium-nitridi/pii kaskadi transistoreilla. Kuormana käytettiin 1 A vakiokuormaa ja tulojännitettä nostettiin asteittain 300 voltista 900 voltiin 100 voltin nostoin. Tulosten mukaan paras hyötysuhde oli 89,6 %, joka mitattiin planaarisella piikarbidi MOSFETilla ja kaivanto piikarbidi MOSFETilla. Pii MOSFETien tapauksessa hyötysuhde oli hieman huonompi, ollen parhaimmillaan 87,7 %. Alhaisilla jännitteillä galliumnitridi/pii kaskadi transistorien hyötysuhde oli verrattavissa piikarbidi MOSFETeihin, mutta hyötysuhde laski jännitettä nostettaessa, ollen lopulta merkittävästi huonompi kuin pii MOSFETeilla

The 2018 GaN Power Electronics Roadmap

Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here

Instrument design and optimization of interferometric reflectance imaging sensors for in vitro diagnostics

Thesis (Ph.D.)--Boston UniversityIn the field of drug discovery and disease diagnostics, protein microarrays have generated much enthusiasm for their high-throughput monitoring of biomarkers; however, this technology has yet to translate from research laboratories to commercialization. The hindrance is the considerable uncertainty and skepticism regarding data obtained. The disparity in results from different laboratories performing identical tests is attributed to a lack of assay quality control. Unlike DNA microarrays, protein microarrays have a higher level of bioreceptor immobilization variability and non-specific binding because of the more complex molecular structure and broader physiochemical properties. Traditional assay detection modalities, such as fluorescence microscopy and surface plasmon resonance, are unable to overcome both of these sources of variation. This dissertation describes the hardware and software design and biological validation of three complementary platforms that overcome bioreceptor variability and non-specific binding for diagnostics. In order to quantify the bioreceptor quality, a label-free, nondestructive, low cost, and high-throughput interferometric sensor has been developed as a quality control tool. The quality control tool was combined with a wide-field fluorescence imaging system to improve fluorescence experimental repeatability. Lastly, a novel high-throughput and label-free platform for quality control and specific protein microarray detection is described. This platform overcomes the additional complexities and time required with labeled assays by discriminating between specific and nonspecific detection by including sizing of individual binding events. Protein microarrays may one day emerge as routine clinical laboratory tests; however, it is important that the proper quality control procedures are in place to minimize erroneous results. These platforms provide reliable and repeatable protein microarray measurements for new advancements in disease diagnostics with the potential for drug discovery

Status and Trend of Power Semiconductor Module Packaging for Electric Vehicles

Power semiconductor modules are the core components in power-train system of hybrid and electric vehicles (HEV/EV). With the global interests and efforts to popularize HEV/EV, automotive module has become one of the fast growing sectors of power semiconductor industry. However, the comprehensive requirements in power, frequency, efficiency, robustness, reliability, weight, volume, and cost of automotive module are stringent than industrial products due to extremely high standards of vehicle safety and harsh environment. The development of automotive power module is facing comprehensive challenges in designing of structure, material, and assembly technology. In this chapter, the status and trend of power semiconductor module packaging for HEV/EV are investigated. Firstly, the functionality of power electronics and module in HEV/EV power-train system, as well as the performance requirements by automotive industry, is addressed. A general overview of HEV/EV module design and manufacturing is discussed. Then, the typical state-of-the-art commercial and custom HEV/EV power modules are reviewed and evaluated. Lastly, the packaging trends of automotive module are investigated. The advanced assembly concept and technology are beneficial to thermal management, minimized parasitic parameters, enhancement of thermal and mechanical reliability, and the reduction of weight, volume, and cost