Ternary Max-Min algebra with application to reversible logic synthesis

Ternary reversible circuits are 0.63 times more compact than equivalent binary reversible circuits and are suitable for low-power implementations. Two notable previous works on ternary reversible circuit synthesis are the ternary Galois field sum of products (TGFSOP) expression-based method and the ternary Max-Min algebra-based method. These methods require high quantum cost and large number of ancilla inputs. To address these problems we develop an alternative ternary Max-Min algebra-based method, where ternary logic functions are represented as Max-Min expressions and realized using our proposed multiple-controlled unary gates. We also show realizations of multiple-controlled unary gates using elementary quantum gates. We develop a method for minimization of ternary Max-Min expressions of up to four variables using ternary K-maps. Finally, we develop a hybrid Genetic Algorithm (HGA)-based method for the synthesis of ternary reversible circuits. The HGA has been tested with 24 ternary benchmark functions with up to five variables. On average our method reduces quantum cost by 41.36% and requires 35.72% fewer ancilla inputs than the TGFSOP-based method. Our method also requires 74.39% fewer ancilla inputs than the previous ternary Max-Min algebra-based method

Optimal NOR Networks for Self-Dual Functions

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryJoint Services Electronics Program / DAAB-07-72-C-025

On The Design Of Low-Complexity High-Speed Arithmetic Circuits In Quantum-Dot Cellular Automata Nanotechnology

For the last four decades, the implementation of very large-scale integrated systems has largely based on complementary metal-oxide semiconductor (CMOS) technology. However, this technology has reached its physical limitations. Emerging nanoscale technologies such as quantum-dot cellular automata (QCA), single electron tunneling (SET), and tunneling phase logic (TPL) are major candidate for possible replacements of CMOS. These nanotechnologies use majority and/or minority logic and inverters as circuit primitives. In this dissertation, a comprehensive methodology for majority/minority logic networks synthesis is developed. This method is capable of processing any arbitrary multi-output Boolean function to nd its equivalent optimal majority logic network targeting to optimize either the number of gates or levels. The proposed method results in different primary equivalent majority expression networks. However, the most optimized network will be generated as a nal solution. The obtained results for 15 MCNC benchmark circuits show that when the number of majority gates is the rst optimization priority, there is an average reduction of 45.3% in the number of gates and 15.1% in the number of levels. They also show that when the rst priority is the number of levels, an average reduction of 23.5% in the number of levels and 43.1% in the number of gates is possible, compared to the majority AND/OR mapping method. These results are better compared to those obtained from the best existing methods. In this dissertation, our approach is to exploit QCA technology because of its capability to implement high-density, very high-speed switching and tremendously lowpower integrated systems and is more amenable to digital circuits design. In particular, we have developed algorithms for the QCA designs of various single- and multi-operation arithmetic arrays. Even though, majority/minority logic are the basic units in promising nanotechnologies, an XOR function can be constructed in QCA as a single device. The basic cells of the proposed arrays are developed based on the fundamental logic devices in QCA and a single-layer structure of the three-input XOR function. This process leads to QCA arithmetic circuits with better results in view of dierent aspects such as cell count, area, and latency, compared to their best counterparts. The proposed arrays can be formed in a pipeline manner to perform the arithmetic operations for any number of bits which could be quite valuable while considering the future design of large-scale QCA circuits

Variable-threshold-mixed-weight threshold element

A threshold element (TE) is a mathematical model of a class of logic gates. The desirability of a threshold element in the application of digital systems stems from its richness of logic power and its relative economy. On the other hand, the tighter tolerences required by the threshold logic element as compared to conventional logic gates have prevented them from being utilized extensively. The purpose of this thesis is to propose a versatile threshold element having high noise immunity and loose tolerance requirement. The proposed TE which has variable threshold and mixed weight capability uses current switching to enhance noise immunity and a differential amplifier voltage comparator to obtain the versatility. The threshold of TE can be varied by a digitally controlled signal to generate a wide spectrum of output functions Practical applications of the designed circuit are included along with sensitivity-investigation --Abstract, page ii

Logic Synthesis for Established and Emerging Computing

Logic synthesis is an enabling technology to realize integrated computing systems, and it entails solving computationally intractable problems through a plurality of heuristic techniques. A recent push toward further formalization of synthesis problems has shown to be very useful toward both attempting to solve some logic problems exactly--which is computationally possible for instances of limited size today--as well as creating new and more powerful heuristics based on problem decomposition. Moreover, technological advances including nanodevices, optical computing, and quantum and quantum cellular computing require new and specific synthesis flows to assess feasibility and scalability. This review highlights recent progress in logic synthesis and optimization, describing models, data structures, and algorithms, with specific emphasis on both design quality and emerging technologies. Example applications and results of novel techniques to established and emerging technologies are reported

Advances in Functional Decomposition: Theory and Applications

Functional decomposition aims at finding efficient representations for Boolean functions. It is used in many applications, including multi-level logic synthesis, formal verification, and testing. This dissertation presents novel heuristic algorithms for functional decomposition. These algorithms take advantage of suitable representations of the Boolean functions in order to be efficient. The first two algorithms compute simple-disjoint and disjoint-support decompositions. They are based on representing the target function by a Reduced Ordered Binary Decision Diagram (BDD). Unlike other BDD-based algorithms, the presented ones can deal with larger target functions and produce more decompositions without requiring expensive manipulations of the representation, particularly BDD reordering. The third algorithm also finds disjoint-support decompositions, but it is based on a technique which integrates circuit graph analysis and BDD-based decomposition. The combination of the two approaches results in an algorithm which is more robust than a purely BDD-based one, and that improves both the quality of the results and the running time. The fourth algorithm uses circuit graph analysis to obtain non-disjoint decompositions. We show that the problem of computing non-disjoint decompositions can be reduced to the problem of computing multiple-vertex dominators. We also prove that multiple-vertex dominators can be found in polynomial time. This result is important because there is no known polynomial time algorithm for computing all non-disjoint decompositions of a Boolean function. The fifth algorithm provides an efficient means to decompose a function at the circuit graph level, by using information derived from a BDD representation. This is done without the expensive circuit re-synthesis normally associated with BDD-based decomposition approaches. Finally we present two publications that resulted from the many detours we have taken along the winding path of our research

Cadd - On-line synthesis of logic circuits

CADD on-line programming system for logic circuit synthesi

Threshold elements and the design of sequential switching networks

Includes bibliographies."AD 657370."[by] A.K. Susskind, D.R. Haring [and] C.L. Liu