Minimum Disturbance Rerouting to Optimize Bandwidth Usage

International audienceDynamic traffic leads to bandwidth fragmentation, which drastically reduces network performance, resulting in increased blocking rate and reduced bandwidth usage. When rerouting traffic flows at Layer 3 of an optical network, network operators are interested in minimizing the disturbances in order to satisfy their Service Level Agreements. Therefore, they turn to the Make-Before-Break (MBB) paradigm.In this paper, we revisit MBB rerouting with the objective of identifying the reroute sequence planning that minimizes the number of reroutes in order to minimize the resource usage. We propose a Dantzig-Wolfe decomposition mathematical model to solve this complex rerouting problem. We instigate how multiple or parallel rerouting reduces the overall minimum number of rerouting events (shortest makespan), and achieve the best resource usage. Numerical results bring interesting insights on that question and show a computational time reduction by about one order of magnitude over the state of the art

Routing on the Channel Dependency Graph:: A New Approach to Deadlock-Free, Destination-Based, High-Performance Routing for Lossless Interconnection Networks

In the pursuit for ever-increasing compute power, and with Moore's law slowly coming to an end, high-performance computing started to scale-out to larger systems. Alongside the increasing system size, the interconnection network is growing to accommodate and connect tens of thousands of compute nodes. These networks have a large influence on total cost, application performance, energy consumption, and overall system efficiency of the supercomputer. Unfortunately, state-of-the-art routing algorithms, which define the packet paths through the network, do not utilize this important resource efficiently. Topology-aware routing algorithms become increasingly inapplicable, due to irregular topologies, which either are irregular by design, or most often a result of hardware failures. Exchanging faulty network components potentially requires whole system downtime further increasing the cost of the failure. This management approach becomes more and more impractical due to the scale of today's networks and the accompanying steady decrease of the mean time between failures. Alternative methods of operating and maintaining these high-performance interconnects, both in terms of hardware- and software-management, are necessary to mitigate negative effects experienced by scientific applications executed on the supercomputer. However, existing topology-agnostic routing algorithms either suffer from poor load balancing or are not bounded in the number of virtual channels needed to resolve deadlocks in the routing tables. Using the fail-in-place strategy, a well-established method for storage systems to repair only critical component failures, is a feasible solution for current and future HPC interconnects as well as other large-scale installations such as data center networks. Although, an appropriate combination of topology and routing algorithm is required to minimize the throughput degradation for the entire system. This thesis contributes a network simulation toolchain to facilitate the process of finding a suitable combination, either during system design or while it is in operation. On top of this foundation, a key contribution is a novel scheduling-aware routing, which reduces fault-induced throughput degradation while improving overall network utilization. The scheduling-aware routing performs frequent property preserving routing updates to optimize the path balancing for simultaneously running batch jobs. The increased deployment of lossless interconnection networks, in conjunction with fail-in-place modes of operation and topology-agnostic, scheduling-aware routing algorithms, necessitates new solutions to solve the routing-deadlock problem. Therefore, this thesis further advances the state-of-the-art by introducing a novel concept of routing on the channel dependency graph, which allows the design of an universally applicable destination-based routing capable of optimizing the path balancing without exceeding a given number of virtual channels, which are a common hardware limitation. This disruptive innovation enables implicit deadlock-avoidance during path calculation, instead of solving both problems separately as all previous solutions

Design Methods and Tools for Application-Specific Predictable Networks-on-Chip

As the complexity of applications grows with each new generation, so does the demand for computation power. To satisfy the computation demands at manageable power levels, we see a shift in the design paradigm from single processor systems to Multiprocessor Systems-on-Chip (MPSoCs). MPSoCs leverage the parallelism in applications to increase the performance at the same power levels. To further improve the computation to power consumption ratio, MPSoCs for embedded applications are heterogeneous and integrate cores that are specialized to perform the different functionalities of the application. With technology scaling, wire power consumption is increasing compared to logic, making communication as expensive as computation. Therefore customizing the interconnect is necessary to achieve energy efficiency. Designing an optimal application specific Network-on-Chip (NoC), that meets application demands, requires the exploration of a large design space. Automatic design and optimization of the NoC is required in order to achieve fast design closure, especially for heterogeneous MPSoCs. To continue to meet the computation requirements of future applications new technologies are emerging. Three dimensional integration promises to increase the number of transistors by stacking multiple silicon layers. This will lead to an increase in the number of cores of the MPSoCs resulting in increased communication demands. To compensate for the increase in the wire delay in new technology nodes as well as to reduce the power consumption further, multi-synchronous design is becoming popular. With multiple clock signals, different parts of the MPSoC can be clocked at different frequencies according to the current demands of the application and can even be shutdown when they are not used at all. This further complicates the design of the NoC.Many applications require different levels of guarantee from the NoC in order to perform their functionality correctly. As communication traffic patterns become more complex, the performance of the NoC can no longer be predicted statically. Therefore designing the interconnect network requires that such guarantees are provided during the dynamic operation of the system which includes the interaction with major subsystems (i.e., main memory) and not just the interconnect itself. In this thesis, I present novel methods to design application-specific NoCs that meet performance demands, under the constraints of new technologies. To provide different levels of Quality of Service, I integrate methods to estimate the NoC performance during the design phase of the interconnect topology. I present methods and architectures for NoCs to efficiently access memory systems, in order to achieve predictable operation of the systems from the point of view of the communication as well as the bottleneck target devices. Therefore the main contribution of the thesis is twofold: scientific as I propose new algorithms to perform topology synthesis and engineering by presenting extensive experiments and architectures for NoC design

Modeling and optimizing the evacuation of hospitals based on the RCPSP with resource transfers

Partial or complete hospital evacuations might become necessary in various situations, e.g. due to a natural disaster such as a flood, due to an internal danger such as a fire, or, as it is frequently the case in Germany, due to the disposal of an aircraft bomb from World War II. In all of these situations, patients have to be evacuated from their locations inside the hospital to safety zones. Unlike in other evacuation problems where people can often help themselves to a certain degree, the same does not hold for this problem. In particular, many patients require assistance in order to reach the safety zones. Despite this additional challenge, only a limited amount of papers have been published that deal with the problem of evacuation planning for hospitals or other healthcare facilities. The problem of hospital evacuations is considered in this thesis in order to estimate the time required to evacuate all patients. In particular, the goal is to find a schedule minimizing the time required for the evacuation of all patients from their initial locations inside the hospital to safety zones inside or outside the hospital while taking into account the available assistants and aids as well as the infrastructure of the hospital. This problem is modeled as a multi-mode resource-constrained project scheduling problem with resource transfers and blockings as well as the makespan objective function. After the model has been presented, a first solution approach based on priority rules is proposed for this problem. For this approach, it is shown that an optimal solution may not always be contained in the considered solution space due to resource transfers of assistants and aids. As a result of this observation, the resource-constrained project scheduling problem with firstand second-tier resource transfers is considered and a solution approach is presented for this problem. For this, a solution representation based on resource flows as well as modifications based on this solution representation are introduced. Furthermore, some theoretical results related to the solution representation as well as the resulting neighborhoods have been developed. In particular, it is shown that for every project a resource flow exists that represents an optimal solution. Also, some results concerning the connectivity of the neighborhoods are presented. Afterward, a second solution approach for the problem of hospital evacuations is proposed in which solutions are represented as resource flows. Finally, computational results are reported for both, the solution approach for the resource-constrained project scheduling problem with first- and second-tier resource transfers as well as for the two solution approaches for the problem of hospital evacuations. For both of these problems, the results show that the solution approaches based on resource flows are able to obtain good solutions in a limited amount of time.Verschiedene Situationen können dazu führen, dass ein Krankenhaus ganz oder teilweise geräumt werden muss. Bei solchen Situationen kann es sich z.B. um eine Naturkatastrophe (z.B. eine Flut), um eine Gefahr innerhalb des Krankenhauses (z.B. ein Feuer) oder um die Entschärfung einer Fliegerbombe aus dem zweiten Weltkrieg handeln. In all diesen Situationen müssen Patienten aus den betroffenen Bereichen des Krankenhauses in sichere Zonen evakuiert werden. Im Gegensatz zu anderen Evakuierungsproblemen können sich Patienten dabei nicht immer aus eigener Kraft in Sicherheit bringen sondern sind auf Unterstützung angewiesen. Bisher wurde das Problem der Evakuierung von Krankenhäusern oder anderen Pflegeeinrichtungen in der Literatur jedoch kaum betrachtet. In dieser Arbeit wird das Problem der Evakuierung von Krankenhäusern mit dem Ziel betrachtet, die benötigte Zeit zur Evakuierung aller Patienten abzuschätzen. Insbesondere sollen Pläne generiert werden, welche die zur Evakuierung aller Patienten benötigte Zeit minimieren. Die Patienten müssen dabei mit Hilfe der verfügbaren Hilfsmittel und Hilfskräfte in Sicherheit gebracht werden. Weiterhin wird die Infrastruktur des Krankenhauses berücksichtigt. In dieser Arbeit wird dieses Problem als ein Mehrmodus ressourcenbeschränktes Projektplanungsproblem mit Ressourcentransfers und Blockierungen sowie der Zielfunktion, die maximale Bearbeitungsdauer zu minimieren, modelliert. Ein erster Lösungsansatz für dieses Problem basiert auf Prioritätsregeln. Für diesen Ansatz kann jedoch gezeigt werden, dass sich aufgrund der Ressourcentransfers nicht immer eine optimale Lösung im betrachteten Lösungsraum befindet. Aus diesem Grund wird das ressourcenbeschränkte Projektplanungsproblem mit Ressourcentransfers erster und zweiter Ordnung näher betrachtet und ein Lösungsansatz basierend auf Ressourcenflüssen für dieses Problem eingeführt. Dabei werden vor allem die Lösungsrepräsentation sowie Modifikationen von Ressourcenflüssen vorgestellt und theoretische Ergebnisse erarbeitet. Insbesondere wird gezeigt, dass für jedes Projekt ein Ressourcenfluss existiert, welcher eine optimale Lösung darstellt. Weiterhin werden einige Ergebnisse zum Zusammenhang der Nachbarschaften vorgestellt. Danach wird ein zweiter Lösungsansatz basierend auf Ressourcenflüssen für das Problem der Evakuierung von Krankenhäusern eingeführt. Abschließend werden Rechenergebnisse für die verschiedenen Lösungsansätze angegeben, welche für das Problem der Evakuierung von Krankenhäusern sowie für das ressourcenbeschränkte Projektplanungsproblem mit Ressourcentransfers erster und zweiter Ordnung entwickelt wurden. Dabei ergibt sich, dass Lösungsansätze basierend auf Ressourcenflüssen in der Lage sind, innerhalb kurzer Zeit gute Ergebnisse zu erzielen

Logical Time for Decentralized Control of Material Handling Systems

The fourth industrial revolution aims to transform production systems. In this work, Logical Time which is a control principle for distributed systems is transferred to material handling systems with decentralized control. The GridSorter, a modular sorter with grid-like structure, is chosen as showcase system. The system is proven to be deadlock-free and is robust against varying transport times. The time-window-based route reservation process is described as Iterative Deepening A*

Decompose and Conquer: Addressing Evasive Errors in Systems on Chip

Modern computer chips comprise many components, including microprocessor cores, memory modules, on-chip networks, and accelerators. Such system-on-chip (SoC) designs are deployed in a variety of computing devices: from internet-of-things, to smartphones, to personal computers, to data centers. In this dissertation, we discuss evasive errors in SoC designs and how these errors can be addressed efficiently. In particular, we focus on two types of errors: design bugs and permanent faults. Design bugs originate from the limited amount of time allowed for design verification and validation. Thus, they are often found in functional features that are rarely activated. Complete functional verification, which can eliminate design bugs, is extremely time-consuming, thus impractical in modern complex SoC designs. Permanent faults are caused by failures of fragile transistors in nano-scale semiconductor manufacturing processes. Indeed, weak transistors may wear out unexpectedly within the lifespan of the design. Hardware structures that reduce the occurrence of permanent faults incur significant silicon area or performance overheads, thus they are infeasible for most cost-sensitive SoC designs. To tackle and overcome these evasive errors efficiently, we propose to leverage the principle of decomposition to lower the complexity of the software analysis or the hardware structures involved. To this end, we present several decomposition techniques, specific to major SoC components. We first focus on microprocessor cores, by presenting a lightweight bug-masking analysis that decomposes a program into individual instructions to identify if a design bug would be masked by the program's execution. We then move to memory subsystems: there, we offer an efficient memory consistency testing framework to detect buggy memory-ordering behaviors, which decomposes the memory-ordering graph into small components based on incremental differences. We also propose a microarchitectural patching solution for memory subsystem bugs, which augments each core node with a small distributed programmable logic, instead of including a global patching module. In the context of on-chip networks, we propose two routing reconfiguration algorithms that bypass faulty network resources. The first computes short-term routes in a distributed fashion, localized to the fault region. The second decomposes application-aware routing computation into simple routing rules so to quickly find deadlock-free, application-optimized routes in a fault-ridden network. Finally, we consider general accelerator modules in SoC designs. When a system includes many accelerators, there are a variety of interactions among them that must be verified to catch buggy interactions. To this end, we decompose such inter-module communication into basic interaction elements, which can be reassembled into new, interesting tests. Overall, we show that the decomposition of complex software algorithms and hardware structures can significantly reduce overheads: up to three orders of magnitude in the bug-masking analysis and the application-aware routing, approximately 50 times in the routing reconfiguration latency, and 5 times on average in the memory-ordering graph checking. These overhead reductions come with losses in error coverage: 23% undetected bug-masking incidents, 39% non-patchable memory bugs, and occasionally we overlook rare patterns of multiple faults. In this dissertation, we discuss the ideas and their trade-offs, and present future research directions.PHDComputer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147637/1/doowon_1.pd

Doctor of Philosophy

dissertationRecent breakthroughs in silicon photonics technology are enabling the integration of optical devices into silicon-based semiconductor processes. Photonics technology enables high-speed, high-bandwidth, and high-fidelity communications on the chip-scale-an important development in an increasingly communications-oriented semiconductor world. Significant developments in silicon photonic manufacturing and integration are also enabling investigations into applications beyond that of traditional telecom: sensing, filtering, signal processing, quantum technology-and even optical computing. In effect, we are now seeing a convergence of communications and computation, where the traditional roles of optics and microelectronics are becoming blurred. As the applications for opto-electronic integrated circuits (OEICs) are developed, and manufacturing capabilities expand, design support is necessary to fully exploit the potential of this optics technology. Such design support for moving beyond custom-design to automated synthesis and optimization is not well developed. Scalability requires abstractions, which in turn enables and requires the use of optimization algorithms and design methodology flows. Design automation represents an opportunity to take OEIC design to a larger scale, facilitating design-space exploration, and laying the foundation for current and future optical applications-thus fully realizing the potential of this technology. This dissertation proposes design automation for integrated optic system design. Using a buildingblock model for optical devices, we provide an EDA-inspired design flow and methodologies for optical design automation. Underlying these flows and methodologies are new supporting techniques in behavioral and physical synthesis, as well as device-resynthesis techniques for thermal-aware system integration. We also provide modeling for optical devices and determine optimization and constraint parameters that guide the automation techniques. Our techniques and methodologies are then applied to the design and optimization of optical circuits and devices. Experimental results are analyzed to evaluate their efficacy. We conclude with discussions on the contributions and limitations of the approaches in the context of optical design automation, and describe the tremendous opportunities for future research in design automation for integrated optics

Train scheduling with application to the UK rail network

Nowadays, transforming the railway industry for better performance and making the best usage of the current capacity are the key issues in many countries. Operational research methods and in particular scheduling techniques have a substantial potential to offer algorithmic solutions to improve railway operation and control. This thesis looks at train scheduling and rescheduling problems in a microscopic level with regard to the track topology. All of the timetable components are fixed and we aim to minimize delay by considering a tardiness objective function and only allowing changes to the order and to the starting times of trains on blocks. Various operational and safety constraints should be considered. We have achieved further developments in the field including generalizations to the existing models in order to obtain a generic model that includes important additional constraints. We make use of the analogy between the train scheduling problem and job shop scheduling problem. The model is customized to the UK railway network and signaling system. Introduced solution methods are inspired by the successful results of the shifting bottleneck to solve the job shop scheduling problems. Several solution methods such as mathematical programming and different variants of the shifting bottleneck are investigated. The proposed methods are implemented on a real-world case study based on London Bridge area in the South East of the UK. It is a dense network of interconnected lines and complicated with regard to stations and junctions structure. Computational experiments show the efficiency and limitations of the mathematical programming model and one variant of the proposed shifting bottleneck algorithms. This study also addresses train routing and rerouting problems in a mesoscopic level regarding relaxing some of the detailed constraints. The aim is to make the best usage of routing options in the network to minimize delay propagation. In addition to train routes, train entry times and orders on track segment are defined. Hence, the routing and scheduling decisions are combined in the solutions arising from this problem. Train routing and rerouting problems are formulated as modified job shop problems to include the main safety and operational constraints. Novel shifting bottleneck algorithms are provided to solve the problem. Computational results are reported on the same case study based on London Bridge area and the results show the efficiency of one variant of the developed shifting bottleneck algorithms in terms of solution quality and runtime

Space station data system analysis/architecture study. Task 2: Options development, DR-5. Volume 2: Design options

The primary objective of Task 2 is the development of an information base that will support the conduct of trade studies and provide sufficient data to make key design/programmatic decisions. This includes: (1) the establishment of option categories that are most likely to influence Space Station Data System (SSDS) definition; (2) the identification of preferred options in each category; and (3) the characterization of these options with respect to performance attributes, constraints, cost and risk. This volume contains the options development for the design category. This category comprises alternative structures, configurations and techniques that can be used to develop designs that are responsive to the SSDS requirements. The specific areas discussed are software, including data base management and distributed operating systems; system architecture, including fault tolerance and system growth/automation/autonomy and system interfaces; time management; and system security/privacy. Also discussed are space communications and local area networking