A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

Fault-tolerance techniques for hybrid CMOS/nanoarchitecture

The authors propose two fault-tolerance techniques for hybrid CMOS/nanoarchitecture implementing logic functions as look-up tables. The authors compare the efficiency of the proposed techniques with recently reported methods that use single coding schemes in tolerating high fault rates in nanoscale fabrics. Both proposed techniques are based on error correcting codes to tackle different fault rates. In the first technique, the authors implement a combined two-dimensional coding scheme using Hamming and Bose-Chaudhuri-Hocquenghem (BCH) codes to address fault rates greater than 5. In the second technique, Hamming coding is complemented with bad line exclusion technique to tolerate fault rates higher than the first proposed technique (up to 20). The authors have also estimated the improvement that can be achieved in the circuit reliability in the presence of Don-t Care Conditions. The area, latency and energy costs of the proposed techniques were also estimated in the CMOS domain

Fine-grained fault-tolerance : reliability as a fungible resource

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 131-134).The traditional design of logic circuits, based on reliable components, is incompatible with the next generation of devices relying on fewer resources and subject to high rates of soft errors. These allow a trade-off between failure probability and their space and power consumption. Using this, we show that reliability can be a fungible resource, interconvertible with other physical resources in multiple, unusual ways, via fault-tolerant architectures. This thesis investigates the potentialities offered by a fault-tolerant design in devices whose reliability is limited by shrinking resources. Surprisingly, we find that an appropriate use of structured redundancy could lead to more efficient components. The performance of a fine-grained multiplexed design can indeed be systematically evaluated in terms of resource savings and reliability improvement. This analysis is applied to characterize technologies at the nano scale, such as molecular electronics, which may benefit enormously by fault-tolerant designs.by François Impens.S.M

Tagged repair techniques for defect tolerance in hybrid nano/CMOS architecture

We propose two new repair techniques for hybrid nano/CMOS computing architecture with lookup table based Boolean logic. Our proposed techniques use tagging mechanism to provide high level of defect tolerance and we present theoretical equations to predict the repair capability including an estimate of the repair cost. The repair techniques are efficient in utilization of spare units and capable of targeting upto 20% defect rates, which is higher than recently reported repair techniques

Optimal microscale water cooled heat sinks for targeted alleviation of hotspot in microprocessors

This paper was presented at the 4th Micro and Nano Flows Conference (MNF2014), which was held at University College, London, UK. The conference was organised by Brunel University and supported by the Italian Union of Thermofluiddynamics, IPEM, the Process Intensification Network, the Institution of Mechanical Engineers, the Heat Transfer Society, HEXAG - the Heat Exchange Action Group, and the Energy Institute, ASME Press, LCN London Centre for Nanotechnology, UCL University College London, UCL Engineering, the International NanoScience Community, www.nanopaprika.eu.Hotspots in microprocessors arise due to non-uniform utilization of the underlying integrated circuits during chip operation. Conventional liquid cooling using microchannels leads to undercooling of the hotspot areas and overcooling of the background area of the chip resulting in excessive temperature gradients across the chip. These in turn adversely affect the chip performance and reliability. This problem becomes even more acute in multi-core processors where most of the processing power is concentrated in specific regions of the chip called as cores. We present a 1-dimensional model for quick design of a microchannel heat sink for targeted, single-phase liquid cooling of hotspots in microprocessors. The method utilizes simplifying assumptions and analytical equations to arrive at the first estimate of a microchannel heat sink design that distributes the cooling capacity of the heat sink by adapting the coolant flow and microchannel size distributions to the microprocessor power map. This distributed cooling in turn minimizes the chip temperature gradient. The method is formulated to generate a heat sink design for an arbitrary chip power map and hence can be readily utilized for different chip architectures. It involves optimization of microchannel widths for various zones of the chip power map under the operational constraints of maximum pressure drop limit for the heat sink. Additionally, it ensures that the coolant flows uninterrupted through its entire travel length consisting of microchannels of varying widths. The resulting first design estimate significantly reduces the computational effort involved in any subsequent CFD analysis required to fine tune the design for more complex flow situations arising, for example, in manifold microchannel heat sinks

Correlation of micro and nano–scale defects with WVTR for aluminium oxide barrier coatings for flexible photovoltaic modules

This paper seeks to establish a correlation between surface topographical defects and water vapour transmission rate (WVTR) measured under laboratory conditions for aluminium–oxide (Al2O3) barrier film employed in flexible photovoltaic (PV) modules. Defects in the barrier layers of PV modules causing high WVTR are not well characterised and understood. A WVTR of ~10−1 g/m2/day is sufficient for the most packaging applications, but ≤10−6 g/m2/day is required for the encapsulation of long–life flexible PV modules (Carcia et al., 2010a, 2010b). In this study, surface metrology techniques along with scanning electron microscopy (SEM) were used for a quantitative characterisation of the barrier film defects. The investigation have provided clear evidence for the correlation of surface defect density and the transmission of water vapour through the barrier coating layer. The outcomes would appear to suggest that small numbers of large defects are the dominant factor in determining WVTR for these barrier layers