Interpretability and complexity of design in the creation of fuzzy logic systems: a user study

In recent years, researchers have become increasingly more interested in designing an interpretable Fuzzy Logic System (FLS). Many studies have claimed that reducing the complexity of FLSs can lead to improved model interpretability. That is, reducing the number of rules tends to reduce the complexity of FLSs, thus improving their interpretability. However, none of these studies have considered interpretability and complexity from human perspectives. Since interpretability is of a subjective nature, it is essential to see how people perceive interpretability and complexity particularly in relation to creating FLSs. Therefore, in this paper we have investigated this issue using an initial user study. This is the first time that a user study has been used to assess the interpretability and complexity of designs in relation to creating FLSs. The user study involved a range of expert practitioners in FLSs and received a diverse set of answers. We are interested to see whether, from the perspectives of people, FLSs are necessarily more interpretable when they are less complex in terms of their design. Although the initial user study is based on small samples (i.e., 25 participants), nevertheless this research provides initial insight into this issue that motivates our future research

Interpretability and complexity of design in the creation of fuzzy logic systems — a user study

In recent years, researchers have become increasingly more interested in designing an interpretable Fuzzy Logic System (FLS). Many studies have claimed that reducing the complexity of FLSs can lead to improved model interpretability. That is, reducing the number of rules tends to reduce the complexity of FLSs, thus improving their interpretability. However, none of these studies have considered interpretability and complexity from human perspectives. Since interpretability is of a subjective nature, it is essential to see how people perceive interpretability and complexity particularly in relation to creating FLSs. Therefore, in this paper we have investigated this issue using an initial user study. This is the first time that a user study has been used to assess the interpretability and complexity of designs in relation to creating FLSs. The user study involved a range of expert practitioners in FLSs and received a diverse set of answers. We are interested to see whether, from the perspectives of people, FLSs are necessarily more interpretable when they are less complex in terms of their design. Although the initial user study is based on small samples (i.e., 25 participants), nevertheless this research provides initial insight into this issue that motivates our future research

Electron Exchange Coupling for Single Donor Solid-State Qubits

Inter-valley interference between degenerate conduction band minima has been shown to lead to oscillations in the exchange energy between neighbouring phosphorus donor electron states in silicon \cite{Koiller02,Koiller02A}. These same effects lead to an extreme sensitivity of the exchange energy on the relative orientation of the donor atoms, an issue of crucial importance in the construction silicon-based spin quantum computers. In this article we calculate the donor electron exchange coupling as a function of donor position incorporating the full Bloch structure of the Kohn-Luttinger electron wavefunctions. It is found that due to the rapidly oscillating nature of the terms they produce, the periodic part of the Bloch functions can be safely ignored in the Heitler-London integrals as was done by Koiller et. al. [Phys. Rev. Lett. 88,027903(2002),Phys. Rev. B. 66,115201(2002)], significantly reducing the complexity of calculations. We address issues of fabrication and calculate the expected exchange coupling between neighbouring donors that have been implanted into the silicon substrate using an 15keV ion beam in the so-called 'top down' fabrication scheme for a Kane solid-state quantum computer. In addition we calculate the exchange coupling as a function of the voltage bias on control gates used to manipulate the electron wavefunctions and implement quantum logic operations in the Kane proposal, and find that these gate biases can be used to both increase and decrease the magnitude of the exchange coupling between neighbouring donor electrons. The zero-bias results reconfirm those previously obtained by Koiller.Comment: 10 Pages, 8 Figures. To appear in Physical Review

Interpretability and complexity of design in the creation of fuzzy logic systems: a user study

In recent years, researchers have become increasingly more interested in designing an interpretable Fuzzy Logic System (FLS). Many studies have claimed that reducing the complexity of FLSs can lead to improved model interpretability. That is, reducing the number of rules tends to reduce the complexity of FLSs, thus improving their interpretability. However, none of these studies have considered interpretability and complexity from human perspectives. Since interpretability is of a subjective nature, it is essential to see how people perceive interpretability and complexity particularly in relation to creating FLSs. Therefore, in this paper we have investigated this issue using an initial user study. This is the first time that a user study has been used to assess the interpretability and complexity of designs in relation to creating FLSs. The user study involved a range of expert practitioners in FLSs and received a diverse set of answers. We are interested to see whether, from the perspectives of people, FLSs are necessarily more interpretable when they are less complex in terms of their design. Although the initial user study is based on small samples (i.e., 25 participants), nevertheless this research provides initial insight into this issue that motivates our future research

Low-complexity distributed issue queue

As technology evolves, power density significantly increases and cooling systems become more complex and expensive. The issue logic is one of the processor hotspots and, at the same time, its latency is crucial for the processor performance. We present a low-complexity FP issue logic (MB/spl I.bar/distr) that achieves high performance with small energy requirements. The MB/spl I.bar/distr scheme is based on classifying instructions and dispatching them into a set of queues depending on their data dependences. These instructions are selected for issuing based on an estimation of when their operands will be available, so the conventional wakeup activity is not required. Additionally, the functional units are distributed across the different queues. The energy required by the proposed scheme is substantially lower than that required by a conventional issue design, even if the latter has the ability of waking-up only unready operands. MB/spl I.bar/distr scheme reduces the energy-delay product by 35% and the energy-delay product by 18% with respect to a state-of-the-art approach.Peer ReviewedPostprint (published version

Cross-layer Balanced and Reliable Opportunistic Routing Algorithm for Mobile Ad Hoc Networks

For improving the efficiency and the reliability of the opportunistic routing algorithm, in this paper, we propose the cross-layer and reliable opportunistic routing algorithm (CBRT) for Mobile Ad Hoc Networks, which introduces the improved efficiency fuzzy logic and humoral regulation inspired topology control into the opportunistic routing algorithm. In CBRT, the inputs of the fuzzy logic system are the relative variance (rv) of the metrics rather than the values of the metrics, which reduces the number of fuzzy rules dramatically. Moreover, the number of fuzzy rules does not increase when the number of inputs increases. For reducing the control cost, in CBRT, the node degree in the candidate relays set is a range rather than a constant number. The nodes are divided into different categories based on their node degree in the candidate relays set. The nodes adjust their transmission range based on which categories that they belong to. Additionally, for investigating the effection of the node mobility on routing performance, we propose a link lifetime prediction algorithm which takes both the moving speed and moving direction into account. In CBRT, the source node determines the relaying priorities of the relaying nodes based on their utilities. The relaying node which the utility is large will have high priority to relay the data packet. By these innovations, the network performance in CBRT is much better than that in ExOR, however, the computation complexity is not increased in CBRT.Comment: 14 pages, 17 figures, 31 formulas, IEEE Sensors Journal, 201

Multiplicative-Additive Proof Equivalence is Logspace-complete, via Binary Decision Trees

Given a logic presented in a sequent calculus, a natural question is that of equivalence of proofs: to determine whether two given proofs are equated by any denotational semantics, ie any categorical interpretation of the logic compatible with its cut-elimination procedure. This notion can usually be captured syntactically by a set of rule permutations. Very generally, proofnets can be defined as combinatorial objects which provide canonical representatives of equivalence classes of proofs. In particular, the existence of proof nets for a logic provides a solution to the equivalence problem of this logic. In certain fragments of linear logic, it is possible to give a notion of proofnet with good computational properties, making it a suitable representation of proofs for studying the cut-elimination procedure, among other things. It has recently been proved that there cannot be such a notion of proofnets for the multiplicative (with units) fragment of linear logic, due to the equivalence problem for this logic being Pspace-complete. We investigate the multiplicative-additive (without unit) fragment of linear logic and show it is closely related to binary decision trees: we build a representation of proofs based on binary decision trees, reducing proof equivalence to decision tree equivalence, and give a converse encoding of binary decision trees as proofs. We get as our main result that the complexity of the proof equivalence problem of the studied fragment is Logspace-complete.Comment: arXiv admin note: text overlap with arXiv:1502.0199

Reflections on Service Systems Boundaries: A Viable Systems Perspective. The case of the London Borough of Sutton

The aim of this paper is to propose a systems interpretation of the concept of complexity and its implications for a theoretical discussion of the concept of boundary in complex service systems. The proposal highlights the interpretative contribution of a dual perspective of observation that distinguishes between a structure-based view and a systems-based view. When dealing with complexity, the phenomenon under investigation cannot be addressed through management approaches that aim to measure and control it in a vain attempt to find the best solution. Due to the inner nature of complexity, a more rewarding approach to a full understanding of problematic situations should place consolidated management models within a more general interpretation framework that suggests preliminary insights about the real nature of the investigated phenomenon. First, this paper outlines the theoretical background of the literature on service, service systems and complex service systems, providing evidence of the contribution of recent service research advances such as service science and service-dominant logic. Next, the paper focuses on the basic principles of systems thinking to introduce the Viable Systems Approach (vSa) as a general framework of reference for both the investigation and the governance of social organisations. The vSa conceptual framework is adopted for proposing some reflections from a systems perspective in the investigation of the case of the London Borough of Sutton (LBS). The focus is on interpreting the paradoxical situation of an increased fear of crime among LBS residents despite the evidence of reduction in the crime rate. Although the incidence has fallen for most types of crimes, a recent poll confirmed that crime is still rated as the most important issue for residents. Therefore, improving safety and reducing crime remain the top priorities for the Safer Sutton Partnership Service. In short, this study proposes to consider ‘‘reducing the fear of crime in a community’’ as a complex service system

Improving latency tolerance of multithreading through decoupling

The increasing hardware complexity of dynamically scheduled superscalar processors may compromise the scalability of this organization to make an efficient use of future increases in transistor budget. SMT processors, designed over a superscalar core, are therefore directly concerned by this problem. The article presents and evaluates a novel processor microarchitecture which combines two paradigms: simultaneous multithreading and access/execute decoupling. Since its decoupled units issue instructions in order, this architecture is significantly less complex, in terms of critical path delays, than a centralized out-of-order design, and it is more effective for future growth in issue-width and clock speed. We investigate how both techniques complement each other. Since decoupling features an excellent memory latency hiding efficiency, the large amount of parallelism exploited by multithreading may be used to hide the latency of functional units and keep them fully utilized. The study shows that, by adding decoupling to a multithreaded architecture, fewer threads are needed to achieve maximum throughput. Therefore, in addition to the obvious hardware complexity reduction, it places lower demands on the memory system. The study also reveals that multithreading by itself exhibits little memory latency tolerance. Results suggest that most of the latency hiding effectiveness of SMT architectures comes from the dynamic scheduling. On the other hand, decoupling is very effective at hiding memory latency. An increase in the cache miss penalty from 1 to 32 cycles reduces the performance of a 4-context multithreaded decoupled processor by less than 2 percent. For the nondecoupled multithreaded processor, the loss of performance is about 23 percent.Peer ReviewedPostprint (published version