101 research outputs found
Design, analysis and optimization of a dynamically reconfi gurable regenerative comparator for ultra-low power 6-bit TC-ADCs in 90nm CMOS technology
In this work the threshold configurable regenerative comparator on which TC-ADCs are based is optimized to further reduce the power consumption for use in battery-less biomedical sensor applications.\nMoreover, the effect of device mismatches on the offset, gain and linearity errors of the ADC is analyzed by means of Monte Carlo simulations.\nThis optimized comparator reduces the power consumption from 13uW to 3uW, while maintaining the same full scale rang
Low-Noise Energy-Efficient Sensor Interface Circuits
Today, the Internet of Things (IoT) refers to a concept of connecting any devices on network where environmental data around us is collected by sensors and shared across platforms. The IoT devices often have small form factors and limited battery capacity; they call for low-power, low-noise sensor interface circuits to achieve high resolution and long battery life. This dissertation focuses on CMOS sensor interface circuit techniques for a MEMS capacitive pressure sensor, thermopile array, and capacitive microphone.
Ambient pressure is measured in the form of capacitance. This work propose two capacitance-to-digital converters (CDC): a dual-slope CDC employs an energy efficient charge subtraction and dual comparator scheme; an incremental zoom-in CDC largely reduces oversampling ratio by using 9b zoom-in SAR, significantly improving conversion energy.
An infrared gesture recognition system-on-chip is then proposed. A hand emits infrared radiation, and it forms an image on a thermopile array. The signal is amplified by a low-noise instrumentation chopper amplifier, filtered by a low-power 30Hz LPF to remove out-band noise including the chopper frequency and its harmonics, and digitized by an ADC. Finally, a motion history image based DSP analyzes the waveform to detect specific hand gestures.
Lastly, a microphone preamplifier represents one key challenge in enabling voice interfaces, which are expected to play a dominant role in future IoT devices. A newly proposed switched-bias preamplifier uses switched-MOSFET to reduce 1/f noise inherently.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137061/1/chaseoh_1.pd
Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor
Due to the switch from CCD to CMOS technology, CMOS based image sensors have become
smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart
from the extensive set of applications requiring image sensors, the next technological
breakthrough in imaging would be to consolidate and completely shift the conventional CMOS
image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative
technology in the imaging field, allowing multiple silicon tiers with different functions to be
stacked on top of each other. The technology allows for an extreme parallelism of the pixel
readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked
image sensor, and the parallelism of the readout can remain constant at any spatial resolution of
the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor
array resolution.
The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked
image sensors, structured with parallel readout circuitries. The readout circuit’s key
requirements are low noise, speed, low-area (for higher parallelism), and low power.
A CMOS imaging review is presented through a short historical background, followed by the
description of the motivation, the research goals, and the work contributions. The fundamentals
of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features,
the essential building blocks, types of operation, as well as their physical characteristics and their
evaluation metrics. Following up on this, the document pays attention to the readout circuit’s
noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron
noise imagers. Lastly, the fabricated test CIS device performances are reported along with
conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future
work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores
CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que
requerem sensores de imagem, o próximo salto tecnológico no ramo dos sensores de imagem é
o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a
tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia
inovadora no campo dos sensores de imagem, permitindo vários planos de silício com diferentes
funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um
paralelismo extremo na leitura dos sinais vindos da matriz de píxeis. Além disso, num sensor de
imagem de planos de silício empilhados, os circuitos de leitura estão posicionados debaixo da
matriz de píxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer
resolução espacial, permitindo assim atingir um extremo baixo ruído e um alto debito de
imagens, virtualmente para qualquer resolução desejada.
O objetivo deste trabalho é o de desenhar circuitos de leitura de coluna de muito baixo ruído,
planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas
altamente paralelizadas. Os requisitos chave para os circuitos de leitura são de baixo ruído,
rapidez e pouca área utilizada, de forma a obter-se o melhor rácio.
Uma breve revisão histórica dos sensores de imagem CMOS é apresentada, seguida da
motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem
CMOS são também abordados para expor as suas características, os blocos essenciais, os tipos
de operação, assim como as suas características físicas e suas métricas de avaliação. No
seguimento disto, especial atenção é dada à teoria subjacente ao ruído inerente dos circuitos de
leitura e dos conversores de coluna, servindo para identificar os possíveis aspetos que dificultem
atingir a tão desejada performance de muito baixo ruído. Por fim, os resultados experimentais
do sensor desenvolvido são apresentados junto com possíveis conjeturas e respetivas conclusões,
terminando o documento com o assunto de empilhamento vertical de camadas de silício, junto
com o possível trabalho futuro
Improving Accuracy and Energy Efficiency of Pipeline Analog to Digital Converters
Analog-to-Digital converters (ADC) are key building blocks of analog and mixed-signal processing that link the natural world of analog signals and the world of digital processing. This work describes the analysis, design, development and test of novel high-resolution (≥12-bit), moderate speed (10-100MS/s), energy-efficient ADCs. Such ADCs are typically used for communication, imaging and video applications.
CMOS process scaling is typically aimed at enabling fast, low-power digital circuits. Scaling leads to lower supply voltages, and to short channel devices with low gain and poor matching between small devices. On the other hand, to process and amplify analog signals analog circuits rely on wide signal swing, large transistor gain and good component matching. Hence, analog circuit performance has lagged far behind digital performance. Analog circuits such as ADCs are therefore nowadays performance bottlenecks in many electronic systems.
The pipeline ADC is a popular architecture for implementing ADCs with a wide range of speed and resolution. This work aims to improve the accuracy and energy efficiency of the pipeline architecture by combining it with more accurate or more energy efficient architectures such as Sigma-Delta and Successive-Approximation (SAR). Such novel, hybrid architectures are investigated in this work.
In the first design, a new architecture is developed which combines a low-OSR resetting Sigma-Delta modulator architecture with the pipeline architecture. This architecture enhances the accuracy and energy efficiency of the pipeline architecture. A prototype 14-bit 23MS/s ADC, based on this new architecture, is designed and tested. This ADC achieves calibration-free 14-bit linearity, 11.7-bit ENOB and 87dB SFDR while dissipating only 48mW of power.
In the second design, new hybrid architecture based on SAR and pipeline architecture is developed. This architecture significantly improves the energy efficiency of the pipeline architecture. A prototype 12-bit 50MS/s ADC is designed based on this new architecture. “Half-gain” and “half-reference” pipeline stages are also introduced in this prototype for the first time to further reduce power dissipation. This ADC dissipates only 3.5mW power.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/76025/1/leechun_1.pd
Contribution to time domain readout circuits design for multi-standard sensing system for low voltage supply and high-resolution applications
Mención Internacional en el título de doctorThis research activity has the purpose of open new possibilities in the design of capacitance-to-digital converters (CDCs) by developing a solution based on time domain conversion. This can be applied to applications related with the Internet-of-Things (IoT). These applications are present in any electronic devices where sensing is needed. To be able to reduce the area of the whole system with the required performance, micro-electromechanical systems (MEMS) sensors are used in these applications. We propose a new family of sensor readout electronics to be integrated with MEMS sensors.
Within the time domain converters, Dual Slope (DS) topology is very interesting to explore a new compromise between performances, area and power consumption. DS topology has been extensively used in instrumentation. The simplicity and robustness of the blocks inside classical DS converters it is the main advantage. However, they are not efficient for applications where higher bandwidth is required. To extend the bandwidth, DS converters have been introduced into ΔΣ loops. This topology has been named as integrating converters. They increase the bandwidth compare to classical DS architecture but at the expense of higher complexity. In this work we propose the use of a new family of DS converters that keep the advantages of the classical architecture and introduce noise shaping. This way the bandwidth is increased without extra blocks. The Self-Compensated noise-shaped DS converter (the name given to the new topology) keeps the signal transfer function (STF) and the noise transfer function (NTF) of Integrating converters. However, we introduce a new arrangement in the core of the converter to do noise shaping without extra circuitry. This way the simplicity of the architecture is preserved.
We propose to use the Self-Compensated DS converter as a CDC for MEMS sensors. This work makes a study of the best possible integration of the two blocks to keep the signal integrity considering the electromechanical behavior of the sensor.
The purpose of this front-end is to be connected to any kind of capacitive MEMS sensor. However, to prove the concepts developed in this thesis the architecture has been connected to a pressure MEMS sensor.
An experimental prototype was implemented in 130-nm CMOS process using the architecture mentioned before. A peak SNR of 103.9 dB (equivalent to 1Pa) has been achieved within a time measurement of 20 ms. The final prototype has a power consumption of 220 μW with an effective area of 0.317 mm2. The designed architecture shows good performance having competitive numbers against high resolution topologies in amplitude domain.Esta actividad de investigación tiene el propósito de explorar nuevas posibilidades en el diseño de convertidores de capacitancia a digital (CDC) mediante el desarrollo de una solución basada en la conversión en el dominio del tiempo. Estos convertidores se pueden utilizar en aplicaciones relacionadas con el mercado del Internet-de-las-cosas (IoT). Hoy en día, estas aplicaciones están presentes en cualquier dispositivo electrónico donde se necesite sensar una magnitud. Para poder reducir el área de todo el sistema con el rendimiento requerido, se utilizan sensores de sistemas micro-electromecánicos (MEMS) en estas aplicaciones. Proponemos una nueva familia de electrónica de acondicionamiento para integrar con sensores MEMS.
Dentro de los convertidores de dominio de tiempo, la topología del doble-rampa (DS) es muy interesante para explorar un nuevo compromiso entre rendimiento, área y consumo de energía. La topología de DS se ha usado ampliamente en instrumentación. La simplicidad y la solidez de los bloques dentro de los convertidores DS clásicos es la principal ventaja. Sin embargo, no son eficientes para aplicaciones donde se requiere mayor ancho de banda. Para ampliar el ancho de banda, los convertidores DS se han introducido en bucles ΔΣ. Esta topología ha sido nombrada como Integrating converters. Esta topología aumenta el ancho de banda en comparación con la arquitectura clásica de DS, pero a expensas de una mayor complejidad. En este trabajo, proponemos el uso de una nueva familia de convertidores DS que mantienen las ventajas de la arquitectura clásica e introducen la configuración del ruido. De esta forma, el ancho de banda aumenta sin bloques adicionales. El convertidor Self-Compensated noise-shaped DS (el nombre dado a la nueva topología) mantiene la función de transferencia de señal (STF) y la función de transferencia de ruido (NTF) de los Integrating converters. Sin embargo, presentamos una nueva topología en el núcleo del convertidor para conformar el ruido sin circuitos adicionales. De esta manera, se preserva la simplicidad de la arquitectura.
Proponemos utilizar el Self-Compensated noise-shaped DS como un CDC para sensores MEMS. Este trabajo hace un estudio de la mejor integración posible de los dos bloques para mantener la integridad de la señal considerando el comportamiento electromecánico del sensor.
El propósito de este circuito de acondicionamiento es conectarse a cualquier tipo de sensor MEMS capacitivo. Sin embargo, para demostrar los conceptos desarrollados en esta tesis, la arquitectura se ha conectado a un sensor MEMS de presión.
Se ha implementado dos prototipos experimentales en un proceso CMOS de 130-nm utilizando la arquitectura mencionada anteriormente. Se ha logrado una relación señal-ruido máxima de 103.9 dB (equivalente a 1 Pa) con un tiempo de medida de 20 ms. El prototipo final tiene un consumo de energía de 220 μW con un área efectiva de 0.317 mm2. La arquitectura diseñada muestra un buen rendimiento comparable con las arquitecturas en el dominio de la amplitud que muestran resoluciones equivalentes.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Pieter Rombouts.- Secretario: Alberto Rodríguez Pérez.- Vocal: Dietmar Strãußnig
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Energy-efficient data converter design in scaled CMOS technology
Data converters bridge the physical and digital worlds. They have been the crucial building blocks in modern electronic systems, and are expected to have a growing significance in the booming era of Internet-of-Things (IoT) and 5G communications. The applications raise energy-efficiency requirements for both low-speed and high-speed converters since they are widely deployed in wireless sensor nodes and portable devices. To explore the solutions, the author worked on three directions: 1) techniques to improve the efficiency of the low-speed converters including the comparator; 2) techniques to develop high-speed data converters including the reference stabilization; 3) new architecture to improve the efficiency of the capacitance-to-digital converter (CDC). In the first part, a power-efficient 10-bit SAR ADC featured with a gain-boosted dynamic comparator is presented. In energy-constrained applications, the converter is usually supplied with low supply voltage (e.g., 0.3 V-0.5 V), which reduces the comparator pre-amplifier (pre-amp) gain and results in higher noise. A novel comparator topology with a dynamic common-gate stage is proposed to increase the pre-amplification gain, thereby reducing noise and offset. Besides, statistical estimation and loading switching techniques are combined to further improve energy efficiency. A 40-nm CMOS prototype achieves a Walden FoM of 1.5 fJ/conversion-step while operating at 100-kS/s from a 0.5-V supply. To further improve the energy-efficiency of the comparator, a novel dynamic pre-amp is proposed. By using an inverter-based input pair powered by a floating reservoir capacitor, the pre-amp realizes both current reuse and dynamic bias, thereby significantly boosting g [subscript m] /I [subscript D] and reducing noise. Moreover, it greatly reduces the influence of the input common-mode (CM) voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180-nm achieves 46-μV input-referred noise while consuming only 1 pJ per comparison under 1.2-V supply, which represents greater than 7 times energy efficiency boost compared to that of a Strong-Arm (SA) latch. The second part of this dissertation focuses on high-speed data converter techniques. A 10-bit high-speed two-stage loop-unrolled SAR ADC is presented. To reduce the SAR logic delay and power, each bit uses a dedicated comparator to store its output and generate an asynchronous clock for the next comparison. To suppress the comparator offset mismatch induced non-linearity, a shared pre-amp are employed in the second fine stage, which is implemented by a dynamic latch to avoid static power consumption. The prototype ADC in 40-nm CMOS achieves 55-dB peak SNDR at 200-MS/s sampling rate without any calibration. A key limiting factor for the SAR ADC to simultaneously achieve high speed and high resolution is the reference ripple settling problem caused by DAC switching. Unlike prior techniques that aim to minimize the reference ripple which requires large reference buffer power or on-chip decoupling capacitance area, this work proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. The prototype 10-bit 120-MS/s SAR ADC is fabricated in 40-nm CMOS process and achieves an SNDR of 55 dB with only 3 pF reference decoupling capacitor. Finally, this dissertation also presents the design of an incremental time-domain two-step CDC. Unlike the classic two-step CDC, this work replaces the OTA-based active-RC integrator with a VCO-based integrator and performs time domain (TD) ΔΣ modulation. The VCO is mostly digital and consumes low power. Featuring the infinite DC gain in phase domain and intrinsic spatial phase quantization, this TDΔΣ enables a CDC design, achieving 85-dB SQNR by having only a 4-bit quantizer, a 1st-order loop and a low OSR of 15. The prototype fabricated in 40-nm CMOS achieves a resolution of 0.29 fF while dissipating only 0.083 nJ per conversion, which improves the energy efficiency by greater than 2 times comparing to that of state-of-the-art CDCsElectrical and Computer Engineerin
Alternative Methods for Non-Linearity Estimation in High-Resolution Analog-to-Digital Converters
The evaluation of the linearity performance of a high resolution Analog-to-
Digital Converter (ADC) by the Standard Histogram method is an outstanding
challenge due to the requirement of high purity of the input signal and
the high number of output data that must be acquired to obtain an acceptable
accuracy on the estimation. These requirements become major application
drawbacks when the measures have to be performed multiple times
within long test flows and for many parts, and under an industrial environment
that seeks to reduce costs and lead times as is the case in the New
Space sector. This thesis introduces two alternative methods that succeed
in relaxing the two previous requirements for the estimation of the Integral
Nonlinearity (INL) parameter in ADCs. The methods have been evaluated
by estimating the Integral Non-Linearity pattern by simulation using realistic
high-resolution ADC models and experimentally by applying them to real
high performance ADCs.
First, the challenge of applying the Standard Histogram method for the
evaluation of static parameters in high resolution ADCs and how the drawbacks
are accentuated in the New Space industry is analysed, being a highly
expensive method for an industrial environment where cost and lead time
reduction is demanded. Several alternative methods to the Standard Histogram
for estimating Integral Nonlinearity in high resolution ADCs are reviewed
and studied. As the number of existing works in the literature is very
large and addressing all of them is a challenge in itself, only those most relevant
to the development of this thesis have been included. Methods based
on spectral processing to reduce the number of data acquired for the linearity
test and methods based on a double histogram to be able to use generators
that do not meet the the purity requirement against the ADC to be tested are
further analysed.
Two novel contributions are presented in this work for the estimation of
the Integral Nonlinearity in ADCs, as possible alternatives to the Standard
Histogram method. The first method, referred to as SSA (Simple Spectral Approach),
seeks to reduce the number of output data that need to be acquired
and focuses on INL estimation using an algorithm based on processing the
spectrum of the output signal when a sinusoidal input stimulus is used. This type of approach requires a much smaller number of samples than the Standard
Histogram method, although the estimation accuracy will depend on
how smooth or abrupt the ADC nonlinearity pattern is. In general, this algorithm
cannot be used to perform a calibration of the ADC nonlinearity error,
but it can be applied to find out between which limits it lies and what its
approximate shape is. The second method, named SDH (Simplified Double
Histogram)aims to estimate the Non-Linearity of the ADC using a poor linearity
generator. The approach uses two histograms constructed from the
two set of output data in response to two identical input signals except for a
dc offset between them. Using a simple adder model, an extended approach
named ESDH (Extended Simplified Double Histogram) addresses and corrects
for possible time drifts during the two data acquisitions, so that it can
be successfully applied in a non-stationary test environment. According to
the experimental results obtained, the proposed algorithm achieves high estimation
accuracy.
Both contributions have been successfully tested in high-resolution ADCs
with both simulated and real laboratory experiments, the latter using a commercial
ADC with 14-bit resolution and 65Msps sampling rate (AD6644 from
Analog Devices).La medida de la característica de linealidad de un convertidor analógicodigital
(ADC) de alta resolución mediante el método estándar del Histograma
constituye un gran desafío debido los requisitos de alta pureza de la señal
de entrada y del elevado número de datos de salida que deben adquirirse
para obtener una precisión aceptable en la estimación. Estos requisitos encuentran
importantes inconvenientes para su aplicación cuando las medidas
deben realizarse dentro de largos flujos de pruebas, múltiples veces y en un
gran número de piezas, y todo bajo un entorno industrial que busca reducir
costes y plazos de entrega como es el caso del sector del Nuevo Espacio. Esta
tesis introduce dos métodos alternativos que consiguen relajar los dos requisitos
anteriores para la estimación de los parámetros de no linealidad en los
ADCs. Los métodos se han evaluado estimando el patrón de No Linealidad
Integral (INL) mediante simulación utilizando modelos realistas de ADC de
alta resolución y experimentalmente aplicándolos en ADCs reales.
Inicialmente se analiza el reto que supone la aplicación del método estándar
del Histograma para la evaluación de los parámetros estáticos en ADCs
de alta resolución y cómo sus inconvenientes se acentúan en la industria del
Nuevo Espacio, siendo un método altamente costoso para un entorno industrial
donde se exige la reducción de costes y plazos de entrega. Se estudian
métodos alternativos al Histograma estándar para la estimación de la No Linealidad
Integral en ADCs de alta resolución. Como el número de trabajos es
muy amplio y abordarlos todos es ya en sí un desafío, se han incluido aquellos
más relevantes para el desarrollo de esta tesis. Se analizan especialmente los métodos basados en el procesamiento espectral para reducir el número
de datos que necesitan ser adquiridos y los métodos basados en un doble
histograma para poder utilizar generadores que no cumplen el requisito de
precisión frente al ADC a medir.
En este trabajo se presentan dos novedosas aportaciones para la estimación
de la No Linealidad Integral en ADCs, como posibles alternativas al método
estándar del Histograma. El primer método, denominado SSA (Simple Spectral
Approach), busca reducir el número de datos de salida que es necesario
adquirir y se centra en la estimación de la INL mediante un algoritmo basado
en el procesamiento del espectro de la señal de salida cuando se utiliza un
estímulo de entrada sinusoidal. Este tipo de enfoque requiere un número
mucho menor de muestras que el método estándar del Histograma, aunque
la precisión de la estimación dependerá de lo suave o abrupto que sea el patrón
de no-linealidad del ADC a medir. En general, este algoritmo no puede
utilizarse para realizar una calibración del error de no linealidad del ADC,
pero puede aplicarse para averiguar entre qué límites se encuentra y cuál
es su forma aproximada. El segundo método, denominado SDH (Simplified
Double Histogram) tiene como objetivo estimar la no linealidad del ADC utilizando
un generador de baja pureza. El algoritmo utiliza dos histogramas,
construidos a partir de dos conjuntos de datos de salida en respuesta a dos
señales de entrada idénticas, excepto por un desplazamiento constante entre
ellas. Utilizando un modelo simple de sumador, un enfoque ampliado denominado
ESDH (Extended Simplified Double Histogram) aborda y corrige
las posibles derivas temporales durante las dos adquisiciones de datos, de
modo que puede aplicarse con éxito en un entorno de prueba no estacionario.
De acuerdo con los resultados experimentales obtenidos, el algoritmo propuesto
alcanza una alta precisión de estimación.
Ambas contribuciones han sido probadas en ADCs de alta resolución
con experimentos tanto simulados como reales en laboratorio, estos últimos
utilizando un ADC comercial con una resolución de 14 bits y una tasa de
muestreo de 65Msps (AD6644 de Analog Devices)
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Active Noise Shaping Analog-to-Digital Data Converters
Successive-approximation-register (SAR) analog-to-digital converters are popular for medium accuracy, medium speed and low power applications, such as in biomedical applications. They have low latency and simple architecture compared with ΔΣ ADCs. This is because of SAR ADCs’ binary searching scheme. Furthermore, SAR ADCs can apply oversampling and noise shaping schemes which are used in ΔΣ ADCs. As a result, the noise-shaping SAR ADC architecture has received more and more attention as a high resolution and power efficient solution for many sensor applications. In this dissertation, novel configurations have been explored for noise-shaping SAR ADCs for power-efficient and high-accuracy data conversion.
Frist, a first-order noise-shaping (NS) SAR ADC using a two-capacitor based DAC (2-C DAC) is described and discussed. There are only two equal valued capacitors used in the DAC, so the total number of capacitors is much less than in conventional binary weighted DAC. Therefore, the 2-C DAC is good for capacitor matching. Furthermore, this 2-C DAC architecture only samples the reference once, so that the proposed NS SAR ADC doesn’t need a reference buffer on or off chip. An active integrator is implemented and used to contribute an ideal first order noise shaping effect and can be extended to second order noise shaping by adding a few extra capacitors with only one integrator. The ADC was fabricated in 180nm CMOS technology. The prototype occupies 0.25mm2. For a 2kHz signal bandwidth, it achieved 78.9dB SNDR and 87.6dB SFDR with a 32 oversampling ratio (OSR). It consumes 74.2 uW power from 1.5V power supply.
Next, a noise shaping SAR ADC with on-chip digital DAC calibration was proposed and implemented. Correlated double sampling (CDS) and correlated level shifting (CLS) are combined to implement the proposed architecture. With these two techniques, the design specifications for the op-amp used in integrator are relaxed. CDS minimized the effect of DC offset and flicker noise from the op-amp, and CLS boosted the effective DC gain of the op-amp. Therefore, the total power consumption of the op-amp can be decreased by about 50% compared with the same NS SAR ADC performance. Also, an incremental ADC (IADC) based on-chip DAC calibration scheme was proposed and implemented. The proposed calibration scheme will share all blocks in the proposed NS SAR ADC, so it will not increase the complexity of the circuitry. The calibration, it gives a more than 13dB improvement on the SNDR. The proposed ADC was fabricated in 130nm CMOS technology. It achieved 85.1 dB DR, 82.6dB SNDR and 90.9dB SFDR with 32 OSR. It consumes 40uW power from 1.6V power supply which gives a 163dB Schreier Figure of Merit
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