Using embedded hardware monitor cores in critical computer systems

The integration of FPGA devices in many different architectures and services makes monitoring and real time detection of errors an important concern in FPGA system design. A monitor is a tool, or a set of tools, that facilitate analytic measurements in observing a given system. The goal of these observations is usually the performance analysis and optimisation, or the surveillance of the system. However, System-on-Chip (SoC) based designs leave few points to attach external tools such as logic analysers. Thus, an embedded error detection core that allows observation of critical system nodes (such as processor cores and buses) should enforce the operation of the FPGA-based system, in order to prevent system failures. The core should not interfere with system performance and must ensure timely detection of errors. This thesis is an investigation onto how a robust hardware-monitoring module can be efficiently integrated in a target PCI board (with FPGA-based application processing features) which is part of a critical computing system. [Continues.

Automated Debugging Methodology for FPGA-based Systems

Electronic devices make up a vital part of our lives. These are seen from mobiles, laptops, computers, home automation, etc. to name a few. The modern designs constitute billions of transistors. However, with this evolution, ensuring that the devices fulfill the designer’s expectation under variable conditions has also become a great challenge. This requires a lot of design time and effort. Whenever an error is encountered, the process is re-started. Hence, it is desired to minimize the number of spins required to achieve an error-free product, as each spin results in loss of time and effort. Software-based simulation systems present the main technique to ensure the verification of the design before fabrication. However, few design errors (bugs) are likely to escape the simulation process. Such bugs subsequently appear during the post-silicon phase. Finding such bugs is time-consuming due to inherent invisibility of the hardware. Instead of software simulation of the design in the pre-silicon phase, post-silicon techniques permit the designers to verify the functionality through the physical implementations of the design. The main benefit of the methodology is that the implemented design in the post-silicon phase runs many order-of-magnitude faster than its counterpart in pre-silicon. This allows the designers to validate their design more exhaustively. This thesis presents five main contributions to enable a fast and automated debugging solution for reconfigurable hardware. During the research work, we used an obstacle avoidance system for robotic vehicles as a use case to illustrate how to apply the proposed debugging solution in practical environments. The first contribution presents a debugging system capable of providing a lossless trace of debugging data which permits a cycle-accurate replay. This methodology ensures capturing permanent as well as intermittent errors in the implemented design. The contribution also describes a solution to enhance hardware observability. It is proposed to utilize processor-configurable concentration networks, employ debug data compression to transmit the data more efficiently, and partially reconfiguring the debugging system at run-time to save the time required for design re-compilation as well as preserve the timing closure. The second contribution presents a solution for communication-centric designs. Furthermore, solutions for designs with multi-clock domains are also discussed. The third contribution presents a priority-based signal selection methodology to identify the signals which can be more helpful during the debugging process. A connectivity generation tool is also presented which can map the identified signals to the debugging system. The fourth contribution presents an automated error detection solution which can help in capturing the permanent as well as intermittent errors without continuous monitoring of debugging data. The proposed solution works for designs even in the absence of golden reference. The fifth contribution proposes to use artificial intelligence for post-silicon debugging. We presented a novel idea of using a recurrent neural network for debugging when a golden reference is present for training the network. Furthermore, the idea was also extended to designs where golden reference is not present

Advanced flight control system study

The architecture, requirements, and system elements of an ultrareliable, advanced flight control system are described. The basic criteria are functional reliability of 10 to the minus 10 power/hour of flight and only 6 month scheduled maintenance. A distributed system architecture is described, including a multiplexed communication system, reliable bus controller, the use of skewed sensor arrays, and actuator interfaces. Test bed and flight evaluation program are proposed

Dynamic Partial Reconfiguration for Dependable Systems

Moore’s law has served as goal and motivation for consumer electronics manufacturers in the last decades. The results in terms of processing power increase in the consumer electronics devices have been mainly achieved due to cost reduction and technology shrinking. However, reducing physical geometries mainly affects the electronic devices’ dependability, making them more sensitive to soft-errors like Single Event Transient (SET) of Single Event Upset (SEU) and hard (permanent) faults, e.g. due to aging effects. Accordingly, safety critical systems often rely on the adoption of old technology nodes, even if they introduce longer design time w.r.t. consumer electronics. In fact, functional safety requirements are increasingly pushing industry in developing innovative methodologies to design high-dependable systems with the required diagnostic coverage. On the other hand commercial off-the-shelf (COTS) devices adoption began to be considered for safety-related systems due to real-time requirements, the need for the implementation of computationally hungry algorithms and lower design costs. In this field FPGA market share is constantly increased, thanks to their flexibility and low non-recurrent engineering costs, making them suitable for a set of safety critical applications with low production volumes. The works presented in this thesis tries to face new dependability issues in modern reconfigurable systems, exploiting their special features to take proper counteractions with low impacton performances, namely Dynamic Partial Reconfiguration

Efficient reconfigurable architectures for 3D medical image compression

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Recently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data through high-bandwidth digital communication lines are of crucial importance. Despite their advantages, most 3-D medical imaging algorithms are computationally intensive with matrix transformation as the most fundamental operation involved in the transform-based methods. Therefore, there is a real need for high-performance systems, whilst keeping architectures exible to allow for quick upgradeability with real-time applications. Moreover, in order to obtain efficient solutions for large medical volumes data, an efficient implementation of these operations is of significant importance. Reconfigurable hardware, in the form of field programmable gate arrays (FPGAs) has been proposed as viable system building block in the construction of high-performance systems at an economical price. Consequently, FPGAs seem an ideal candidate to harness and exploit their inherent advantages such as massive parallelism capabilities, multimillion gate counts, and special low-power packages. The key achievements of the work presented in this thesis are summarised as follows. Two architectures for 3-D Haar wavelet transform (HWT) have been proposed based on transpose-based computation and partial reconfiguration suitable for 3-D medical imaging applications. These applications require continuous hardware servicing, and as a result dynamic partial reconfiguration (DPR) has been introduced. Comparative study for both non-partial and partial reconfiguration implementation has shown that DPR offers many advantages and leads to a compelling solution for implementing computationally intensive applications such as 3-D medical image compression. Using DPR, several large systems are mapped to small hardware resources, and the area, power consumption as well as maximum frequency are optimised and improved. Moreover, an FPGA-based architecture of the finite Radon transform (FRAT)with three design strategies has been proposed: direct implementation of pseudo-code with a sequential or pipelined description, and block random access memory (BRAM)- based method. An analysis with various medical imaging modalities has been carried out. Results obtained for image de-noising implementation using FRAT exhibits promising results in reducing Gaussian white noise in medical images. In terms of hardware implementation, promising trade-offs on maximum frequency, throughput and area are also achieved. Furthermore, a novel hardware implementation of 3-D medical image compression system with context-based adaptive variable length coding (CAVLC) has been proposed. An evaluation of the 3-D integer transform (IT) and the discrete wavelet transform (DWT) with lifting scheme (LS) for transform blocks reveal that 3-D IT demonstrates better computational complexity than the 3-D DWT, whilst the 3-D DWT with LS exhibits a lossless compression that is significantly useful for medical image compression. Additionally, an architecture of CAVLC that is capable of compressing high-definition (HD) images in real-time without any buffer between the quantiser and the entropy coder is proposed. Through a judicious parallelisation, promising results have been obtained with limited resources. In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.Ministry of Higher Education Malaysia (MOHE), Universiti Tun Hussein Onn Malaysia (UTHM) and the British Counci

FPGA-Based Testbed for Fault Injection on SHA-256

In real world applications, cryptographic algorithms are implemented in hardware or software on specific devices. An active attacker may inject faults during the computation process and careful analysis of faulty results can potentially leak secret information. These kinds of attacks known as fault injection attacks may have devastating effects in the field of hardware and embedded cryptography. This research proposes a partial implementation of SHA-256 along with an onboard fault injection circuit implemented on an FPGA. The proposed fault injection circuit is used to generate glitches in the clock to induce a setup time violation in the circuit and thereby produce error(s) in the output. The main objective of this research is to study the viability of fault injection using the clock glitches on the SHA-256

RIM: Reconfigurable Instruction Memory Hierarchy for Embedded Systems

Ph.DDOCTOR OF PHILOSOPH

Aeronautical Engineering: A Continuing Bibliography with indexes

This bibliography lists 426 reports, articles and other documents introduced into the NASA scientific and technical information system in August 1984. Reports are cited in the area of Aeronautical Engineering. The coverage includes documents on the engineering and theoretical aspects of design, construction, evaluation, testing operation and performance of aircraft (including aircraft engines) and associated components, equipment and systems

Pem fuel cell modeling and converters design for a 48 v dc power bus

Fuel cells (FC) are electrochemical devices that directly convert the chemical energy of a fuel into electricity. Power systems based on proton exchange membrane fuel cell (PEMFC) technology have been the object of increasing attention in recent years as they appear very promising in both stationary and mobile applications due to their high efficiency, low operating temperature allowing fast startup, high power density, solid electrolyte, long cell and stack life, low corrosion, excellent dynamic response with respect to the other FCs, and nonpolluting emissions to the environment if the hydrogen is obtained from renewable sources. The output-voltage characteristic in a PEMFC is limited by the mechanical devices which are used for regulating the air flow in its cathode, the hydrogen flow in its anode, its inner temperature, and the humidity of the air supplied to it. Usually, the FC time constants are dominated by the fuel delivery system, in particular by the slow dynamics of the compressor responsible for supplying the oxygen. As a consequence, a fast load transient demand could cause a high voltage drop in a short time known as oxygen starvation phenomenon that is harmful for the FC. Thus, FCs are considered as a slow dynamic response equipment with respect to the load transient requirements. Therefore, batteries, ultracapacitors or other auxiliary power sources are needed to support the operation of the FC in order to ensure a fast response to any load power transient. The resulting systems, known as FC hybrid systems, can limit the slope of the current or the power generated by the FC with the use of current-controlled dc-dc converters. In this way, the reactant gas starvation phenomena can be avoided and the system can operate with higher efficiency. The purpose of this thesis is the design of a DC-DC converter suitable to interconnect all the different elements in a PEMFC-hybrid 48-V DC bus. Since the converter could be placed between elements with very different voltage levels, a buck-boost structure has been selected. Especially to fulfill the low ripple requirements of the PEMFCs, but also those of the auxiliary storage elements and loads, our structure has inductors in series at both its input and its output. Magnetically coupling these inductors and adding a damping network to its intermediate capacitor we have designed an easily controllable converter with second-order-buck-like dominant dynamics. This new proposed topology has high efficiency and wide bandwidth acting either as a voltage or as a current regulator. The magnetic coupling allows to control with similar performances the input or the output inductor currents. This characteristic is very useful because the designed current-controlled converter is able to withstand shortcircuits at its output and, when connected to the FC, it facilitates to regulate the current extracted from the FC to avoid the oxygen starvation phenomenon. Testing in a safe way the converter connected to the FC required to build an FC simulator that was subsequently improved by developing an emulator that offered real-time processing and oxygen-starvation indication. To study the developed converters and emulators with different brands of PEMFCs it was necessary to reactivate long-time inactive Palcan FCs. Since the results provided by the manual reactivation procedure were unsatisfactory, an automatic reactivation system has been developed as a complementary study of the thesis.En esta tesis se avanzo en el diseño de un bus DC de 48 V que utiliza como elemento principal de generación de energía eléctrica una pila de combustible. Debido a que la dinámica de las pilas de combustible están limitadas por sus elementos mecánicos auxiliares de control una variación rápida de una carga conectada a ella puede ocasionar daños. Es por esto que es necesario utilizar elementos almacenadores de energía que puedan suministrar estas rápidas variaciones de carga y convertidores para que gestionen de una forma controlada la potencia del bus DC. Durante la realización de pruebas de los convertidores es de gran importancia utilizar emuladores o simuladores de pilas de combustibles, esto nos permite de una forma económica y segura realizar pruebas criticas antes de conectar los convertidores a la pila. Adicionalmente una nueva topologia de convertidor fue presentada y ésta gestionará la potencia en el bu