VLSI Architectures and Rapid Prototyping Testbeds for Wireless Systems

The rapid evolution of wireless access is creating an ever changing variety of standards for indoor and outdoor environments. The real-time processing demands of wireless data rates in excess of 100 Mbps is a challenging problem for architecture design and verification. In this paper, we consider current trends in VLSI architecture and in rapid prototyping testbeds to evaluate these systems. The key phases in multi-standard system design and prototyping include: Algorithm Mapping to Parallel Architectures – based on the real-time data and sampling rate and the resulting area, time and power complexity; Configurable Mappings and Design Exploration – based on heterogeneous architectures consisting of DSP, programmable application-specific instruction (ASIP) processors, and co-processors; and Verification and Testbed Integration – based on prototype implementation on programmable devices and integration with RF units.Nokia Foundation FellowshipNokia CorporationNational InstrumentsNational Science Foundatio

Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology

Many very-high-complexity signal processing algorithms are required in future wireless systems, giving tremendous challenges to real-time implementations. In this paper, we present our industrial rapid prototyping experiences on 3G/4G wireless systems using advanced signal processing algorithms in MIMO-CDMA and MIMO-OFDM systems. Core system design issues are studied and advanced receiver algorithms suitable for implementation are proposed for synchronization, MIMO equalization, and detection. We then present VLSI-oriented complexity reduction schemes and demonstrate how to interact these high-complexity algorithms with an HLS-based methodology for extensive design space exploration. This is achieved by abstracting the main effort from hardware iterations to the algorithmic C/C++ fixed-point design. We also analyze the advantages and limitations of the methodology. Our industrial design experience demonstrates that it is possible to enable an extensive architectural analysis in a short-time frame using HLS methodology, which significantly shortens the time to market for wireless systems.National Science Foundatio

FPGA design methodology for industrial control systems—a review

This paper reviews the state of the art of fieldprogrammable gate array (FPGA) design methodologies with a focus on industrial control system applications. This paper starts with an overview of FPGA technology development, followed by a presentation of design methodologies, development tools and relevant CAD environments, including the use of portable hardware description languages and system level programming/design tools. They enable a holistic functional approach with the major advantage of setting up a unique modeling and evaluation environment for complete industrial electronics systems. Three main design rules are then presented. These are algorithm refinement, modularity, and systematic search for the best compromise between the control performance and the architectural constraints. An overview of contributions and limits of FPGAs is also given, followed by a short survey of FPGA-based intelligent controllers for modern industrial systems. Finally, two complete and timely case studies are presented to illustrate the benefits of an FPGA implementation when using the proposed system modeling and design methodology. These consist of the direct torque control for induction motor drives and the control of a diesel-driven synchronous stand-alone generator with the help of fuzzy logic

Modelling Heterogeneous DSP–FPGA Based System Partitioning with Extensions to the Spinach Simulation Environment

In this paper we present system-on-a-chip extensions to the Spinach simulation environment for rapidly prototyping heterogeneous DSP/FPGA based architectures, specifically in the embedded domain. This infrastructure has been successfully used to model systems varying from multiprocessor gigabit ethernet controllers to Texas Instruments C6x series DSP based systems with tightly coupled FPGA based coprocessors for computational offloading. As an illustrative example of this toolsets functionality, we investigate workload partitioning in heterogeneous DSP/FPGA based embedded environments. Specifically, we focus on computational offloading of matrix multiplication kernels across DSP/FPGA based embedded architectures

HDS, a real-time multi-DSP motion estimator for MPEG-4 H.264 AVC high definition video encoding

International audienceH.264 AVC video compression standard achieves high compression rates at the cost of a high encoder complexity. The encoder performances are greatly linked to the motion estimation operation which requires high computation power and memory bandwidth. High definition context magnifies the difficulty of a real-time implementation. EPZS and HME are two well-known motion estimation algorithms. Both EPZS and HME are implemented in a DSP and their performances are compared in terms of both quality and complexity. Based on these results, a new algorithm called HDS for Hierarchical Diamond Search is proposed. HDS motion estimation is integrated in a AVC encoder to extract timings and resulting video qualities reached. A real-time DSP implementation of H.264 quarter-pixel accuracy motion estimation is proposed for SD and HD video format. Furthermore HDS characteristics make this algorithm well suited for H.264 SVC real-time encoding applications

An FPGA implementation of OFDM transceiver for LTE applications

The paper presents a real-time transceiver using an Orthogonal Frequency-Division Multiplexing (OFDM) signaling scheme. The transceiver is implemented on a Field- Programmable Gate Array (FPGA) through Xilinx System Generator for DSP and includes all the blocks needed for the transmission path of OFDM. The transmitter frame can be reconfigured for different pilot and data schemes. In the receiver, time-domain synchronization is achieved thr ough a joint maximum likelihood (ML) symbol arrival-time and carrier frequency offset (CFO) estimator through the redundant information contained in the cyclic prefix (CP). A least-squares channel estimation retrieves the channel state information and a simple zero-forcing scheme has been implemented for channel equalization. Results show that a rough implementation of the signal path can be impleme nted by using only Xilinx System Generator for DSP

Computer Architectures to Close the Loop in Real-time Optimization

© 2015 IEEE.Many modern control, automation, signal processing and machine learning applications rely on solving a sequence of optimization problems, which are updated with measurements of a real system that evolves in time. The solutions of each of these optimization problems are then used to make decisions, which may be followed by changing some parameters of the physical system, thereby resulting in a feedback loop between the computing and the physical system. Real-time optimization is not the same as fast optimization, due to the fact that the computation is affected by an uncertain system that evolves in time. The suitability of a design should therefore not be judged from the optimality of a single optimization problem, but based on the evolution of the entire cyber-physical system. The algorithms and hardware used for solving a single optimization problem in the office might therefore be far from ideal when solving a sequence of real-time optimization problems. Instead of there being a single, optimal design, one has to trade-off a number of objectives, including performance, robustness, energy usage, size and cost. We therefore provide here a tutorial introduction to some of the questions and implementation issues that arise in real-time optimization applications. We will concentrate on some of the decisions that have to be made when designing the computing architecture and algorithm and argue that the choice of one informs the other

Rapid Prototyping for Evaluating Vehicular Communications

[Abstract] This Thesis details the different elements of a rapid prototyping system able to implement and evaluate vehicular communications fast, according to the continuously evolving requirements of the industry. The system is basically composed of a testbed and a channel emulator, which allow evaluating communication transceivers in realistic vehicular scenarios. Two different testbeds are introduced: a generic 2x2 system and a vehicular platform. The former is used to compare and study space-time block coding (STBC) transmissions at 2.4 GHz over different indoor channels. The latter makes use of software transceivers whose performance is evaluated when they work under artificial high-speed Rayleigh-fading scenarios. To show the capabilities of both platforms, three software transceivers have been developed following the specifications for the physical layers of the standards IEEE 802.11p, IEEE 802.11a and IEEE 802.16e (Mobile WiMAX). The present work details the different elements that make up each transceiver and indicates how to connect them to the rest of the system to perform evaluation measurements. Finally, single-antenna and multi-antenna performances are measured thanks to the design and implementation of three FPGA-based channel emulators that are able to recreate up to seven different vehicular scenarios that include urban canyons, suburban areas and highways[Resumo] A presente Tese detalla os elementos necesarios para constituir un sistema basado en prototipado rápido capaz de levar a cabo e avaliar comunicacións vehiculares. O hardware do sistema está composto básicamente por unha plataforma de probas (testbed) e un emulador de canal, os cales permiten avaliar o rendemento de transceptores inartiamicos recreando diferentes escenarios vehiculares. Inicialmente, este traballo céntrase na descripción do hardware do sistema, detallando a construcción e proba dunha plataforma multi-antena e un testebed vehicular. Estos sistemas permitiron, respectivamente, estudar o comportamento de códigos STBC (space-time block codes) en interiores e medir o rendemento de tranceptores software ao traballar a distintas velocidades vehiculares en canais con desvaecemento Rayleigh. Tres transceptores software foron creados seguindo as especificacións das capas físicas dos estándares IEEE 802.11p, IEEE 802.11a e IEEE 802.16e (Mobile WiMAX). Este traballo detalla os diferentes componentes de cada transceptor, indicando cómo conectalos ao resto do sistema para realizar a avaliacition do seu rendemento. Dita avaliación realizouse coa axuda de tres emuladores de canal basados en tecnoloxía FPGA (Field Programmable Gate Array), os cales son capaces de recrear ata sete escenarios vehiculares distintos, incluindo cañóns urbanos, zonas suburbanas e autopistas.[Resumen] La presente Tesis detalla los elementos necesarios para constituir un sistema basado en prototipado rtiapido capaz de llevar a cabo y evaluar comunicaciones vehiculares. El hardware del sistema está compuesto por una plataforma de pruebas (testbed) y un emulador de canal, los cuales permiten evaluar el rendimiento de transceptores inaltiambricos recreando diferentes escenarios vehiculares. Inicialmente, este trabajo se centra en la descripcition del hardware del sistema, detallando la construccition y prueba de una plataforma multi-antena y un testebed vehicular. Estos sistemas han permitido, respectivamente, estudiar el comportamiento de ctiodigos STBC (space-time block codes) en interiores y medir el rendimiento en canal con desvanecimiento Rayleigh de tranceptores software a distintas velocidades vehiculares. Tres transceptores software han sido creados siguiendo las especificaciones de las capas físicas de los estandares IEEE 802.11p, IEEE 802.11a e IEEE 802.16e (Mobile WiMAX). Este trabajo detalla los diferentes componentes de cada transceptor, indicando ctiomo conectarlos al resto del sistema para realizar la evaluacition de su rendimiento. Dicha evaluacition se realiztio con la ayuda de tres emuladores de canal basados en FPGAs (Field Programmable Gate Array), los cuales son capaces de recrear comunicaciones multi-antena en hasta siete escenarios vehiculares distintos, incluyendo cañones urbanos, zonas suburbanas y autopistas

MATLAB as a Design and Verification Tool for the Hardware Prototyping of Wireless Communication Systems

Peer ReviewedPostprint (published version