62 research outputs found
On the hardware reduction of z-datapath of vectoring CORDIC
In this article we present a novel design of a hardware optimal vectoring CORDIC processor. We present a mathematical theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z-datapath. Using this technique it is possible to achieve three and 1.5 times reduction in the number of registers and adder respectively compared to conventional CORDIC. Following this, a 16-bit vectoring CORDIC is designed for the application in Synchronizer for IEEE 802.11a standard. The total area and dynamic power consumption of the processor is 0.14 mm2 and 700?W respectively when synthesized in 0.18?m CMOS library which shows its effectiveness as a low-area low-power processor
An approach to the application of shift-and-add algorithms on engineering and industrial processes
Different kinds of algorithms can be chosen so as to compute elementary functions. Among all of them, it is worthwhile mentioning the shift-and-add algorithms due to the fact that they have been specifically designed to be very simple and to save computer resources. In fact, almost the only operations usually involved with these methods are additions and shifts, which can be easily and efficiently performed by a digital processor. Shift-and-add algorithms allow fairly good precision with low cost iterations. The most famous algorithm belonging to this type is CORDIC. CORDIC has the capability of approximating a wide variety of functions with only the help of a slight change in their iterations. In this paper, we will analyze the requirements of some engineering and industrial problems in terms of type of operands and functions to approximate. Then, we will propose the application of shift-and-add algorithms based on CORDIC to these problems. We will make a comparison between the different methods applied in terms of the precision of the results and the number of iterations required.This research was supported by the Conselleria de Educacion of the Valencia Region Government under grant number GV/2011/043
A study and comparison of COordinate Rotation DIgital Computer (CORDIC) architectures
Most of the digital signal processing applications performs operations like
multiplication, addition, square-root calculation, solving linear equations
etc. The physical implementation of these operations consumes a lot of hardware
and, software implementation consumes large memory. Even if they are
implemented in hardware, they do not provide high speed, and due to this
reason, even today the software implementation dominates hardware. For
realizing operations from basic to very complex ones with less hardware, a
Co-ordinate Rotation Digital Computer (CORDIC) proves beneficial. It is capable
of performing mathematical operations right from addition to highly complex
functions with the help of arithmetic unit and shifters only. This paper gives
a brief overview of various existing CORDIC architectures, their working
principle, application domain and a comparison of these architectures.
Different designs are available as per the target, i.e. high accuracy and
precision, low area, low latency, hardware efficient, low power,
reconfigurability, etc. that can be used as per the application in which the
architecture needs to be employed
CORDIC algorithm and its applications
openThe CORDIC (Coordinate Rotation Digital Computer) algorithm is used for solving vast sets of functions such as trigonometric functions, hyperbolic functions and natural logarithms. This thesis is going to discuss how the algorithm works and its architecture implementation. It is also going to explore potential applications of the algorithm in digital communication systems, specifically for the realization of the DDS (Direct Digital Synthesis) and digital modulation.The CORDIC (Coordinate Rotation Digital Computer) algorithm is used for solving vast sets of functions such as trigonometric functions, hyperbolic functions and natural logarithms. This thesis is going to discuss how the algorithm works and its architecture implementation. It is also going to explore potential applications of the algorithm in digital communication systems, specifically for the realization of the DDS (Direct Digital Synthesis) and digital modulation
A fast CORDIC co-processor architecture for digital signal processing applications
The coordinate rotational digital computer (CORDIC) is an arithmetic algorithm, which has been used for arithmetic units in the fast computing of elementary functions and for special purpose hardware in programmable logic devices. This paper describes a classification method that can be used for the possible applications of the algorithm and the architecture that is required for fast hardware computing of the algorithm.Área: Redes - Sistemas Operativos - Sistemas de Tiempo Real - Arquitectura de Procesadore
A fast CORDIC co-processor architecture for digital signal processing applications
The coordinate rotational digital computer (CORDIC) is an arithmetic algorithm, which has been used for arithmetic units in the fast computing of elementary functions and for special purpose hardware in programmable logic devices. This paper describes a classification method that can be used for the possible applications of the algorithm and the architecture that is required for fast hardware computing of the algorithm.Área: Redes - Sistemas Operativos - Sistemas de Tiempo Real - Arquitectura de ProcesadoresRed de Universidades con Carreras en Informática (RedUNCI
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