Compressive image sensor architecture with on-chip measurement matrix generation

A CMOS image sensor architecture that uses a cellular automaton for the pseudo-random compressive sampling matrix generation is presented. The image sensor employs in-pixel pulse-frequency modulation and column wise pulse counters to produce compressed samples. A common problem of compressive sampling applied to image sensors is that the size of a full-frame compressive strategy is too large to be stored in an on-chip memory. Since this matrix has to be transmitted to or from the reconstruction system its size would also prevent practical applications. A full-frame compressive strategy generated using a 1-D cellular automaton showing a class III behavior neither needs a storage memory nor needs to be continuously transmitted. In-pixel pulse frequency modulation and up-down counters allow the generation of differential compressed samples directly in the digital domain where it is easier to improve the required dynamic range. These solutions combined together improve the accuracy of the compressed samples thus improving the performance of any generic reconstruction algorithm.Ministerio de Economía y Competitividad TEC2015-66878-C3-1-RJunta de Andalucía TIC 2338-2013Office of Naval Research (USA) N00014141035

Operation and maintenance manual for universal pfm real-time data-reduction system

Operation and maintenance manual for universal pulse frequency modulation /pfm/ real time data reduction syste

A Pulse Frequency Modulation VCO-ADC in 40nm

This brief describes the architecture and implementation of a novel voltage-controlled oscillator-based analog-to-digital converter (VCO-ADC). Instead of a ring oscillator, the VCO is built with a pulse frequency modulation architecture where an analog feedback loop ensures both oscillation and linearity of the voltage-to-frequency conversion. A multibit first-order noise-shaped output is achieved by sampling a digital delay line that acts as a part of the oscillator and as a multibit quantizer. A prototype has been implemented in a 40-nm CMOS process. Although most of the circuit elements are taken from a standard digital library, a transconductor is required as the input stage. To ensure proper linearity, a bulk-driven transconductor has been designed. The ADC measurements reach 53 dB of SNDR at 1 GHz sampling frequency in a 20-MHz bandwidth with a pseudo-differential architecture. Powered at 1.1 V, the power consumption is 3.5 mW. The active area is 0.08 mm 2 . The resulting figure-of-merit equals 242 fJ/step.This work was supported by the CICYT Projects, Spain, under Grant TEC2014-56879-R and Grant TEC2017-82653-R. This brief was recommended by Associate Editor S. Mirabbasi

Boundary-mode operation of the boost converter for thermoelectric generator maximum power tracking

This article has been made available through the Brunel Open Access Publishing Fund.Performance-favourable and noteworthy characteristics of the Boost converter are reported, when the latter operates in Maximum Power Tracking (MPT) mode, while fed from a fixed internal resistance power source specifically a Thermo Electric Generator (TEG). It is found that if the converter is controlled with Pulse Frequency Modulation (PFM), for a specific value of inductance, the inductor current inherently remains on the boundary of continuity for the whole control range, that is under all conditions, resulting in reduced switching losses. Furthermore, MPT is possible without the sampling of any current but only with the sampling of the converter input and output voltages. The above theoretical findings have been verified by an experimental prototype

Voltage spectrum of an isolated inverter with bipolar pulse frequency modulation

У статті розглянуто інвертор напруги з гальванічною розв’язкою. Показано, що для ефективного використання високочастотного трансформатора, модуляцію напруги доцільно проводити за законом двополярної частотно-імпульсної модуляції з постійною тривалістю імпульсу. У цьому випадку трансформатор перемагнічується по граничній петлі гістерезису і тому за одну комутацію ключових елементів інвертора передається максимальна кількість енергії, що зменшує динамічні втрати у перетворювачі. На виході інвертора напруга, модульована за запропонованим законом, випрямляється і згладжується фільтром, після чого на виході перетворювача формується напруга, близька до синусоїдальної. Основною задачею дослідження є аналіз спектру напруги високочастотного інвертора, модульованої за законом двополярної частотно-імпульсної модуляції, і випрямленої напруги, модульованої за законом однополярної частотно-імпульсної модуляції. Для аналізу спектра напруги запропоновано використовувати ряд Фур’є двох змінних, який дозволяє розділити вплив несучої і модулюючої функції на спектр модульованого сигналу. Оскільки сигнал з частотно-імпульсною модуляцією формується на основі несучої функції зі змінною частотою, його спектр розраховується з використанням функції перетворення змінної часу на основі широтно-імпульсно модульованого сигналу з несучою функцією, що має постійну частоту. Двополярна модуляція отримується шляхом опису двополярного сигналу як суми двох однополярних сигналів – одного з позитивною, іншого – з негативною полярністю. Розрахований спектр модульованого сигналу на виході інвертора свідчить про те, що енергія через високочастотний трансформатор передається в основному на проміжній частоті, що свідчить про ефективне використання трансформатора. Спектр випрямленого однополярного сигналу має яскраво виражену першу гармоніку та низький склад вищих гармонік, що спрощує їх фільтрацію та зменшує габарити фільтра. Отже використання запропонованого закону модуляції на практиці дозволить зменшити габарити високочастотного трансформатора та рівень динамічних втрат через зменшення кількості комутацій ключових елементів інвертора.In this paper describes a voltage inverter with galvanic isolation. It is shown that for efficient use of a high-frequency transformer, it is advisable to perform voltage modulation according to the law of bipolar frequency-pulse modulation with a constant pulse duration. In this case, the transformer is magnetized by the hysteresis limit loop, and therefore the maximum amount of energy is transmitted in one commutation of the inverter switch elements, which reduces the dynamic losses in the converter. At the output of the inverter, the voltage, modulated by the proposed law, is rectified and smoothed by the filter, after which the output of the converter generates a voltage close to sinusoidal. The main objective of the study is to research the voltage spectrum of a high-frequency inverter modulated by the law of bipolar frequency-pulse modulation and rectified voltage, modulated by the law of unipolar frequency-pulse modulation. For the analysis of the voltage spectrum it is proposed to use a Double Fourier series, which allows to divide the influence of the carrier and the modulating function on the spectrum of the modulated signal. Since the frequency-modulated signal is formed on the basis of a variable-frequency carrier function, its spectrum is calculated using a variable-time conversion function based on a pulse-width modulated signal with a constant-frequency carrier function. Bipolar modulation is obtained by describing the bipolar signal as the sum of two unipolar signals - one with a positive and the other with a negative polarity. The calculated spectrum of the modulated signal at the output of the inverter indicates that energy is transmitted mainly through the high-frequency transformer at an intermediate frequency, which indicates the efficient use of the transformer. The rectilinear unipolar signal spectrum is transmitted with first harmonic and a low higher harmonic composition, which simplifies their filtration and reduces filter dimensions. Therefore, the application of the proposed modulation law in practice will reduce the size of the high-frequency transformer and the level of dynamic losses by reducing the commutations of switch elements of the inverte

Oversampled analog-to-digital converter architectures based on pulse frequency modulation

Mención Internacional en el título de doctorThe purpose of this research work is providing new insights in the development of voltage-controlled oscillator based analog-to-digital converters (VCO-based ADCs). Time-encoding based ADCs have become of great interest to the designer community due to the possibility of implementing mostly digital circuits, which are well suited for current deep-submicron CMOS processes. Within this topic, VCO-based ADCs are one of the most promising candidates. VCO-based ADCs have typically been analyzed considering the output phase of the oscillator as a state variable, similar to the state variables considered in __ modulation loops. Although this assumption might take us to functional designs (as verified by literature), it does not take into account neither the oscillation parameters of the VCO nor the deterministic nature of quantization noise. To overcome this issue, we propose an interpretation of these type of systems based on the pulse frequency modulation (PFM) theory. This permits us to analytically calculate the quantization noise, in terms of the working parameters of the system. We also propose a linear model that applies to VCO-based systems. Thanks to it, we can determine the different error processes involved in the digitization of the input data, and the performance limitations which these processes direct to. A generic model for any order open-loop VCO-based ADCs is made based on the PFM theory. However, we will see that only the first-order case and a second order approximation can be implemented in practice. The PFM theory also allows us to propose novel approaches to both single-stage and multistage VCObased architectures. We describe open-loop architectures such as VCO-based architectures with digital precoding, PFM-based architectures that can be used as efficient ADCs or MASH architectures with optimal noise-transfer-function (NTF) zeros. We also make a first approach to the proposal and analysis of closed loop architectures. At the same time, we deal with one of the main limitations of VCOs (especially those built with ring oscillators), which is the non-linear voltage to- frequency relation. In this document, we describe two techniques mitigate this phenomenon. Firstly, we propose to use a pulse width modulator in front of the VCO. This way, there are only two possible oscillation states. Consequently, the oscillator works linearly. To validate the proposed technique, an experimental prototype was implemented in a 40-nm CMOS process. The chip showed noise problems that degraded the expected resolution, but allowed us to verify that the potential performance was close to the expected one. A potential signal-to-noise-distortion ratio (SNDR) equal to 56 dB was achieved in 20 MHz bandwidth, consuming 2.15 mW with an occupied area equal to 0.03 mm2. In comparison to other equivalent systems, the proposed architecture is simpler, while keeping similar power consumption and linearity properties. Secondly, we used a pulse frequency modulator to implement a second ADC. The proposed architecture is intrinsically linear and uses a digital delay line to increase the resolution of the converter. One experimental prototype was implemented in a 40-nm CMOS process using one of these architectures. Proper results were measured from this prototype. These results allowed us to verify that the PFM-based architecture could be used as an efficient ADC. The measured peak SNDR was equal to 53 dB in 20 MHz bandwidth, consuming 3.5 mW with an occupied area equal to 0.08 mm2. The architecture shows a great linearity, and in comparison to related work, it consumes less power and occupies similar area. In general, the theoretical analyses and the architectures proposed in the document are not restricted to any application. Nevertheless, in the case of the experimental chips, the specifications required for these converters were linked to communication applications (e.g. VDSL, VDSL2, or even G.fast), which means medium resolution (9-10 bits), high bandwidth (20 MHz), low power and low area.El propósito del trabajo presentado en este documento es aportar una nueva perspectiva para el diseño de convertidores analógico-digitales basados en osciladores controlados por tensión. Los convertidores analógico-digitales con codificación temporal han llamado la atención durante los últimos años de la comunidad de diseñadores debido a la posibilidad de implementarlos en su gran mayoría con circuitos digitales, los cuales son muy apropiados para los procesos de diseño manométricos. En este ámbito, los convertidores analógico-digitales basados en osciladores controlados por tensión son uno de los candidatos más prometedores. Los convertidores analógico-digitales basados en osciladores controlados por tensión han sido típicamente analizados considerando que la fase del oscilador es una variable de estado similar a las que se observan en los moduladores __. Aunque esta consideración puede llevarnos a diseños funcionales (como se puede apreciar en muchos artículos de la literatura), en ella no se tiene en cuenta ni los parámetros de oscilación ni la naturaleza determinística del ruido de cuantificación. Para solventar esta cuestión, en este documento se propone una interpretación alternativa de este tipo de sistemas haciendo uso de la teoría de la modulación por frecuencia de pulsos. Esto nos permite calcular de forma analítica las ecuaciones que modelan el ruido de cuantificación en función de los parámetros de oscilación. Se propone también un modelo lineal para el análisis de convertidores analógico-digitales basados en osciladores controlados por tensión. Este modelo permite determinar las diferentes fuentes de error que se producen durante el proceso de digitalización de los datos de entrada y las limitaciones que suponen. Un modelo genérico de convertidor de cualquier orden se propone con la ayuda de este modelo. Sin embargo, solo los casos de primer orden y una aproximación al caso de segundo orden se pueden implementar en la práctica. La teoría de la modulación por frecuencia de pulsos también permite nuevas perspectivas para la propuesta y el análisis tanto de arquitecturas de una sola etapa como de arquitecturas de varias etapas construidas con osciladores controlados por tensión. Se proponen y se describen arquitecturas en lazo abierto como son las basadas en osciladores controlador por tensión con moduladores digitales en la etapa de entrada, moduladores por frecuencia de pulsos que se utilizan como convertidores analógico-digitales eficientes o arquitecturas en cascada en las que se optimizan la distribución de los ceros en la función de transferencia del ruido. También se realiza una aproximación a la propuesta y el análisis de arquitecturas en lazo cerrado. Al mismo tiempo, se aborda una de las problemáticas más importantes de los osciladores controlados por tensión (especialmente en aquellos implementados mediante osciladores en anillo): la relación tensión-freculineal que presentan este tipo de circuitos. En el documento, se describen dos técnicas cuyo objetivo es mitigar esta limitación. La primera técnica de corrección se basa en el uso de un modulador por ancho de pulsos antes del oscilador controlado por tensión. De esta forma, solo existen dos estados de oscilación en el oscilador, se trabaja de forma lineal y no se genera distorsión en los datos de salida. La técnica se propone de forma teórica haciendo uso de la teoría desarrollada previamente. Para llevar a cabo la validación de la propuesta teórica se fabricó un prototipo experimental en un proceso CMOS de 40-nm. El chip mostró problemas de ruido que limitaban la resolución, sin embargo, nos permitió velicar que la resolución ideal que se podrá haber obtenido estaba muy cercana a la resolución esperada. Se obtuvo una potencial relación señal-(ruido-distorsión) igual a 56 dB en 20 MHz de ancho de banda, un consumo de 2.15 mW y un área igual a 0.03 mm2. En comparación con sistemas equivalentes, la arquitectura propuesta es más simple al mismo tiempo que se mantiene el consumo así como la linealidad. A continuación, se propone la implementación de un convertidor analógico digital mediante un modulador por frecuencia de pulsos. La arquitectura propuesta es intrínsecamente lineal y hace uso de una línea de retraso digital con el fin de mejorar la resolución del convertidor. Como parte del trabajo experimental, se fabricó otro chip en tecnología CMOS de 40 nm con dicha arquitectura, de la que se obtuvieron resultados notables. Estos resultados permitieron verificar que la arquitectura propuesta, en efecto, podrá emplearse como convertidor analógico-digital eficiente. La arquitectura consigue una relación real señal-(ruido-distorsión) igual a 53 dB en 20 MHz de ancho de banda, un consumo de 3.5 mW y un área igual a 0.08 mm2. Se obtiene una gran linealidad y, en comparación con arquitecturas equivalentes, el consumo es menor mientras que el área ocupada se mantiene similar. En general, las aportaciones propuestas en este documento se pueden aplicar a cualquier tipo de aplicación, independientemente de los requisitos de resolución, ancho de banda, consumo u área. Sin embargo, en el caso de los prototipos fabricados, las especificaciones se relacionan con el ámbito de las comunicaciones (VDSL, VDSL2, o incluso G.fast), en donde se requiere una resolución media (9-10 bits), alto ancho de banda (20 MHz), manteniendo bajo consumo y baja área ocupada.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Michael Peter Kennedy.- Secretario: Antonio Jesús López Martín.- Vocal: Jörg Hauptman

Interfacing PDM sensors with PFM spiking systems: application for Neuromorphic Auditory Sensors

In this paper we present a sub-system to convert audio information from low-power MEMS microphones with pulse density modulation (PDM) output into rate coded spike streams. These spikes represent the input signal of a Neuromorphic Auditory Sensor (NAS), which is implemented with Spike Signal Processing (SSP) building blocks. For this conversion, we have designed a HDL component for FPGA able to interface with PDM microphones and converts their pulses to temporal distributed spikes following a pulse frequency modulation (PFM) scheme with an accurate configurable Inter-Spike-Interval. The new FPGA component has been tested in two scenarios, first as a stand-alone circuit for its characterization, and then it has been integrated with a full NAS design to verify its behavior. This PDM interface demands less than 1% of a Spartan 6 FPGA resources and has a power consumption below 5mW.Ministerio de Economía y Competitividad TEC2016-77785-

AER and dynamic systems co-simulation over Simulink with Xilinx System Generator

Address-Event Representation (AER) is a neuromorphic communication protocol for transferring information of spiking neurons implemented into VLSI chips. These neuro-inspired implementations have been used to design sensor chips (retina, cochleas), processing chips (convolutions, filters) and learning chips, what makes possible the development of complex, multilayer, multichip neuromorphic systems. In biology one of the last steps of the processing is to move a muscle, to apply the results of these complex neuromorphic processing to the real world. One interesting question is to be able to transform, or translate, the AER information into robot movements, like for example, moving a DC motor. This paper presents several ways to translate AER spikes into DC motor power, and to control a DC motor speed, based on Pulse Frequency Modulation. These methods have been simulated into Simulink with Xilinx System Generator, and tested into the AER-Robot platform.Junta de Andalucía P06-TIC-01417Ministerio de Educación y Ciencia TEC2006-11730-C03-0

Single-Flux-Quantum Bipolar Digital-to-Analog Converter Comprising Polarity-Switchable Double-Flux-Quantum Amplifier

We present a single-flux-quantum (SFQ)-based digital-to-analog converter (DAC) generating bipolar output voltages, in which the key component is a polarity-switchable double-flux-quantum amplifier (PS-DFQA). The DAC comprised a dc/SFQ converter, an 8-bit variable pulse-number-multiplier (PNM), and a 8-fold PS-DFQA integrated on a single chip. SFQ pulse-frequency modulation was employed to realize variable output voltage amplitude, for which the multiplication factor of the variable-PNM was controlled by a commercial data generator situated at room temperature. The variable-PNM realized 8-bit resolution with a multiplication factor between 0 and 255. Bias currents fed to the 8-fold PS-DFQA were polarity-switched in synchronization with the digital code for the variable-PNM. The whole circuits including I/O elements were designed using SFQ cell libraries, and fabricated using a niobium integration process. Sinusoidal bipolar voltage waveform of 0.38 mVpp was demonstrated using a reference signal source of 43.94 MHz