Thermo-mechanical stress measurement and analysis in three dimensional interconnect structures

Three-dimensional (3-D) integration is effective to overcome the wiring limit imposed on device density and performance with continued scaling. The application of TSV (Through-Silicon Via) is essential for 3D IC integration. TSVs are embedded into the silicon substrate to form vertical, electrical connections between stacked IC chips. However, due to the large CTE mismatch between Silicon and Copper, thermal stresses are induced by various thermal histories from the device processing, and they have caused serious concerns regarding the thermal-mechanical reliability. Firstly, a semi-analytic approach is introduced to understand stress distributions in TSV structures. This is followed by application of finite element analysis for more accurate prediction of stress behavior according to the real geometry of the sample. The conventional Raman method is used to measure the linear combination of in-plane stress components near silicon top surface Secondly, the limitation of conventional Raman method is discussed: only certain linear combination of in-plane stress, instead of separate value for each stress components, can be obtained. Two different kinds of innovative Raman measurements have been developed and employed to study the normal stress components separately. Both of them take advantages of different laser polarization profiles to resolve the normal stress components separately based on experimental data. The top-down Raman measurements utilize so called “high NA effect” to obtain additional information, and can resolve all 3 normal stress components. Independent bending beam experiments are used to validate the results from cross-section Raman measurement on the same sample. The correlation between top-down Raman measurement and cross-section Raman measurement are investigated as well. Lastly, as a typical example of 3D IC package, a stack-die memory package is presented. Finite element analysis combined with cross-section Raman measurement and high resolution moiré interferometry were employed to investigate the thermal-mechanical reliability and chip-package interaction of the stack-die memory structure.Physic

Fiabilité de l’underfill et estimation de la durée de vie d’assemblages microélectroniques

Abstract : In order to protect the interconnections in flip-chip packages, an underfill material layer is used to fill the volumes and provide mechanical support between the silicon chip and the substrate. Due to the chip corner geometry and the mismatch of coefficient of thermal expansion (CTE), the underfill suffers from a stress concentration at the chip corners when the temperature is lower than the curing temperature. This stress concentration leads to subsequent mechanical failures in flip-chip packages, such as chip-underfill interfacial delamination and underfill cracking. Local stresses and strains are the most important parameters for understanding the mechanism of underfill failures. As a result, the industry currently relies on the finite element method (FEM) to calculate the stress components, but the FEM may not be accurate enough compared to the actual stresses in underfill. FEM simulations require a careful consideration of important geometrical details and material properties. This thesis proposes a modeling approach that can accurately estimate the underfill delamination areas and crack trajectories, with the following three objectives. The first objective was to develop an experimental technique capable of measuring underfill deformations around the chip corner region. This technique combined confocal microscopy and the digital image correlation (DIC) method to enable tri-dimensional strain measurements at different temperatures, and was named the confocal-DIC technique. This techique was first validated by a theoretical analysis on thermal strains. In a test component similar to a flip-chip package, the strain distribution obtained by the FEM model was in good agreement with the results measured by the confocal-DIC technique, with relative errors less than 20% at chip corners. Then, the second objective was to measure the strain near a crack in underfills. Artificial cracks with lengths of 160 μm and 640 μm were fabricated from the chip corner along the 45° diagonal direction. The confocal-DIC-measured maximum hoop strains and first principal strains were located at the crack front area for both the 160 μm and 640 μm cracks. A crack model was developed using the extended finite element method (XFEM), and the strain distribution in the simulation had the same trend as the experimental results. The distribution of hoop strains were in good agreement with the measured values, when the model element size was smaller than 22 μm to capture the strong strain gradient near the crack tip. The third objective was to propose a modeling approach for underfill delamination and cracking with the effects of manufacturing variables. A deep thermal cycling test was performed on 13 test cells to obtain the reference chip-underfill delamination areas and crack profiles. An artificial neural network (ANN) was trained to relate the effects of manufacturing variables and the number of cycles to first delamination of each cell. The predicted numbers of cycles for all 6 cells in the test dataset were located in the intervals of experimental observations. The growth of delamination was carried out on FEM by evaluating the strain energy amplitude at the interface elements between the chip and underfill. For 5 out of 6 cells in validation, the delamination growth model was consistent with the experimental observations. The cracks in bulk underfill were modelled by XFEM without predefined paths. The directions of edge cracks were in good agreement with the experimental observations, with an error of less than 2.5°. This approach met the goal of the thesis of estimating the underfill initial delamination, areas of delamination and crack paths in actual industrial flip-chip assemblies.Afin de protéger les interconnexions dans les assemblages, une couche de matériau d’underfill est utilisée pour remplir le volume et fournir un support mécanique entre la puce de silicium et le substrat. En raison de la géométrie du coin de puce et de l’écart du coefficient de dilatation thermique (CTE), l’underfill souffre d’une concentration de contraintes dans les coins lorsque la température est inférieure à la température de cuisson. Cette concentration de contraintes conduit à des défaillances mécaniques dans les encapsulations de flip-chip, telles que la délamination interfaciale puce-underfill et la fissuration d’underfill. Les contraintes et déformations locales sont les paramètres les plus importants pour comprendre le mécanisme des ruptures de l’underfill. En conséquent, l’industrie utilise actuellement la méthode des éléments finis (EF) pour calculer les composantes de la contrainte, qui ne sont pas assez précises par rapport aux contraintes actuelles dans l’underfill. Ces simulations nécessitent un examen minutieux de détails géométriques importants et des propriétés des matériaux. Cette thèse vise à proposer une approche de modélisation permettant d’estimer avec précision les zones de délamination et les trajectoires des fissures dans l’underfill, avec les trois objectifs suivants. Le premier objectif est de mettre au point une technique expérimentale capable de mesurer la déformation de l’underfill dans la région du coin de puce. Cette technique, combine la microscopie confocale et la méthode de corrélation des images numériques (DIC) pour permettre des mesures tridimensionnelles des déformations à différentes températures, et a été nommée le technique confocale-DIC. Cette technique a d’abord été validée par une analyse théorique en déformation thermique. Dans un échantillon similaire à un flip-chip, la distribution de la déformation obtenues par le modèle EF était en bon accord avec les résultats de la technique confocal-DIC, avec des erreurs relatives inférieures à 20% au coin de puce. Ensuite, le second objectif est de mesurer la déformation autour d’une fissure dans l’underfill. Des fissures artificielles d’une longueuer de 160 μm et 640 μm ont été fabriquées dans l’underfill vers la direction diagonale de 45°. Les déformations circonférentielles maximales et principale maximale étaient situées aux pointes des fissures correspondantes. Un modèle de fissure a été développé en utilisant la méthode des éléments finis étendue (XFEM), et la distribution des contraintes dans la simuation a montré la même tendance que les résultats expérimentaux. La distribution des déformations circonférentielles maximales était en bon accord avec les valeurs mesurées lorsque la taille des éléments était plus petite que 22 μm, assez petit pour capturer le grand gradient de déformation près de la pointe de fissure. Le troisième objectif était d’apporter une approche de modélisation de la délamination et de la fissuration de l’underfill avec les effets des variables de fabrication. Un test de cyclage thermique a d’abord été effectué sur 13 cellules pour obtenir les zones délaminées entre la puce et l’underfill, et les profils de fissures dans l’underfill, comme référence. Un réseau neuronal artificiel (ANN) a été formé pour établir une liaison entre les effets des variables de fabrication et le nombre de cycles à la délamination pour chaque cellule. Les nombres de cycles prédits pour les 6 cellules de l’ensemble de test étaient situés dans les intervalles d’observations expérimentaux. La croissance de la délamination a été réalisée par l’EF en évaluant l’énergie de la déformation au niveau des éléments interfaciaux entre la puce et l’underfill. Pour 5 des 6 cellules de la validation, le modèle de croissance du délaminage était conforme aux observations expérimentales. Les fissures dans l’underfill ont été modélisées par XFEM sans chemins prédéfinis. Les directions des fissures de bord étaient en bon accord avec les observations expérimentales, avec une erreur inférieure à 2,5°. Cette approche a répondu à la problématique qui consiste à estimer l’initiation des délamination, les zones de délamination et les trajectoires de fissures dans l’underfill pour des flip-chips industriels

An in-situ experimental-numerical approach for interface delamination characterization

Interfacial delamination is a key reliability challenge in composites and microelectronic systems due to (high density) integration of dissimilar materials. Delamination occurs due to significant stresses generated at the interfaces, for instance, caused by thermal cycling due to the mismatch in thermal expansion coefficient and Poisson’s ratio of the adherent layers. Predictive finite element models are generally used to minimize delamination failures during the design and optimization of these materials and systems. Successful prediction, however, requires a relevant interface model that can capture the observed (irreversible) crack initiation and propagation behavior in experiments. To this end, dedicated delamination experiments with in-situ microscopic visualization are needed to identify the relevant delamination mechanism(s) and to accurately measure the interface properties, such as the interface toughness, as a function of mode mixity (i.e. loading angle). Hence, the goal of this research is to develop experimental-numerical tools required for accurate characterization and prediction of interface delamination. As a first step to reach this goal, a novel Miniature Mixed Mode Bending (MMMB) delamination setup, which enables in-situ characterization of interface delamination in miniature multi-layer structures, was designed and realized. This setup employs an inventive loading configuration to sensitively measure global load-displacement delamination curves for the full range of mode mixities from which the interface toughness or Critical Energy Release Rate (CERR) can be determined, while it was designed with sufficiently small dimensions to fit in the chamber of a scanning electron microscope or under an optical microscope for detailed real-time fracture analysis during delamination. The performance of the setup was assessed using dedicated test samples, supported by finite element analyses. The measurement concept was successfully validated on homogeneous bilayer sampleswith a glue interface system. The validation experiments also revealed roomfor improvement of themeasurement accuracy, robustness, and applicability. Therefore, further optimization in the design was performed and an improved version of the MMMB setup was developed. This setup can access a considerably larger range of interface systems, shows significantly higher accuracy and reproducibility in load-displacement measurements, and is more robust. The potential of the new in-situ experimental technique for interface parameter identification was also illustrated. For instance, high resolution in-situ SEM imaging during delamination allows for measurement of the strain maps and crack opening displacement (COD) fields using digital image correlation in addition to the identification of the delamination failure mechanism. In-situ SEM observation of delamination in different interface structures reveals failure mechanisms ranging from interface damage to interface plasticity. Hence, an irreversible model description of the interface behavior that can capture the observed unloading-reloading responses is needed for accurate prediction of, for instance, crack branching and crack propagation at multiple interfaces using predictive finite element models. Therefore, a combined damage and plasticity formulation was presented that is suitable for modeling of the unloading response of an interface ranging from full damage to full plasticity, while it introduces a minimum number of model parameters that can be experimentally determined. The unloading model can be used with the existing mixed-mode cohesive zone laws that describe the interface loading behavior. The relevance and applicability of the unloading model was demonstrated, in combination with the existing improved Xu-Needlemanmixed mode cohesive law, by modeling the observed combined damage-plasticity unloading response of the above-mentioned glue interface system. In addition, a procedure to identify the model parameters has been presented. Permanent deformation of the sample structure often occurs during delamination tests, particularly, if the layers forming the interface are ductile and the interface is strong. Therefore, accurate determination of the interface fracture toughness requires identification and separation of the contribution of structural plasticity to the total energy dissipation, taking into account the presence of plasticity mechanisms within the fracture process zone at the interface that contribute to the interface fracture toughness. To this end, a semi-analytical approach accounting for the structural plasticity in the sample layers was developed, in order to obtain an accurate value of the interface fracture toughness in a mode I experiment. The approach was numerically verified by employing a finite element model with cohesive zone elements (at the interface). The proposed approach was experimentally assessed by characterizing the interface fracture toughness of industrially relevant copper lead framemolding compound epoxy (CuLF-MCE) structures with different layer thicknesses. In summary, the combined application of in-situ MMMB experiments, the analytical procedure to determine the CERR, and the cohesive zone model with the parameter identification procedure allows for accurate characterization of the delamination mechanism(s) and prediction of the interface mechanics. As a demonstration, industrially relevant coated CuLF-MCE and uncoated CuLF-white molding compound (WMC) interface systems have been characterized in detail using the developed experimental tools

End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

A novel entropy production based full-chip TSV fatigue analysis

Through-silicon vias (TSVs) are subject to thermal fatigue due to stress over time, no matter how small the stress is. Existing works on TSV fatigue all rely on measurement-based parameters to estimate the lifetime, and cannot consider detailed thermal profiles. In this paper, we propose a new method for TSV fatigue prediction using entropy production during thermal cycles. By combining thermodynamics and mechanics laws, the fatigue process can be quantitatively evaluated with detailed thermal profiles. Experimental results show that interestingly, the landing pad possesses the most easy-to-fail region, which generates up to 50% more entropy compared with the TSV body. The impact of landing pad dimension and TSV geometries are also studied, providing guidance for reliability enhancement. Finally, full-chip fatigue analysis is performed based on stress superposition. To the best of the authors\u27 knowledge, this is the first TSV fatigue model that is free of measurement data fitting, the first that is capable of considering detailed thermal profiles, and the first framework for efficient full-chip TSV fatigue analysis. --Abstract, page iii

Design and reliability of polymeric packages for high voltage power semiconductors

This thesis focuses on the development of a novel polymer based housing for power thyristor devices typically used in long distance high voltage direct current (HVDC) transmission. Power thyristor devices used in HVDC power conversion stations are typically packaged in a hermetically sealed ceramic housing and have demonstrated an excellent history of reliability and performance. However, to avoid increasing the number of thyristors in future higher powered HVDC schemes thyristors having higher power ratings at 8.5 kV and sizes at 125 mm and 150 mm diameters are sought for implementation to achieve higher transmission ratings of, for example, 4000 A at +/- 800 kV. The main disadvantages of such large ceramic-based packages are higher processing cost and weight whilst robustness is also a concern. To overcome these issues, replacing the current ceramic housing with a polymeric material has been investigated in this project. The advantages it is anticipated such packages will provide include lower cost, less weight, robustness, recyclability, etc. However, some challenges it will also offer are: non-hermeticity i.e. polymers are moisture and gas permeable, potentially more complex manufacturing routes, and different electrical, mechanical and thermal properties compared to ceramic materials. The work presented in this thesis was part of a larger project where these challenges have been addressed by developing and testing a prototype polymeric thyristor housing. The prototype is aimed at demonstrating that polymer packages can deliver performance and reliability comparable to, if not better than, current ceramic packages. In this thesis, it is the package development and reliability related studies that are discussed. Because the housings will experience severe electrical stresses and various thermal excursions during their service life, the electrical and thermo-mechanical behaviour of the polymer housing was studied using finite element analysis to gain an understanding of the effects of various design variables and materials properties on performance and the tradeoffs between performance and manufacturability. From these modelling studies, design guidelines have been established for the future development of polymer housings. On the other hand, to identify the physics-of-failure of the prototype that was manufactured as part of the project, accelerated life tests were performed to study its reliability. The knowledge gained from the polymer prototype development was then applied to the design of a larger 125 mm diameter housing using the Taguchi method of experimental design