Evaluation of SiC Schottky diodes using pressure contacts

The thermomechanical reliability of SiC power devices and modules is increasingly becoming of interest especially for high power applications where power cycling performance is critical. Press-pack assemblies are a trusted and reliable packaging solution that has traditionally been used for high power thyristor- based applications in FACTS/HVDC, although press-pack IGBTs have become commercially available more recently. These press-pack IGBTs require anti-parallel PiN diodes for enabling reverse conduction capability. In these high power applications, paralleling chips for high current conduction capability is a requirement, hence, electrothermal stability during current sharing is critical. SiC Schottky diodes not only exhibit the advantages of wide bandgap technology compared to silicon PiN diodes, but they have significantly lower zero temperature coefficient (ZTC) meaning they are more electrothermally stable. The lower ZTC is due to the unipolar nature of SiC Schottky diodes as opposed to the bipolar nature of PiN diodes. This paper investigates the implementation and reliability of SiC Schottky diodes in press-pack assemblies. The impact of pressure loss on the electrothermal stability of parallel devices is investigated

Methods and Results of Power Cycling Tests for Semiconductor Power Devices

This work intends to enhance the state of the research in power cycling tests with statements on achievable measurement accuracy, proposed test bench topologies and recommendations on improved test strategies for various types of semiconductor power devices. Chapters 1 and 2 describe the current state of the power cycling tests in the context of design for reliability comprising applicable standards and lifetime models. Measurement methods in power cycling tests for the essential physical parameters are explained in chapter 3. The dynamic and static measurement accuracy of voltage, current and temperature are discussed. The feasibly achievable measurement delay tmd of the maximal junction temperature Tjmax, its consequences on accuracy and methods to extrapolate to the time point of the turn-off event are explained. A method to characterize the thermal path of devices to the heatsink via measurements of the thermal impedance Zth is explained. Test bench topologies starting from standard setups, single to multi leg DC benches are discussed in chapter 4. Three application-closer setups implemented by the author are explained. For tests on thyristors a test concept with truncated sinusoidal current waveforms and online temperature measurement is introduced. An inverter-like topology with actively switching IGBTs is presented. In contrast to standard setups, there the devices under test prove switching capability until reaching the end-of-life criteria. Finally, a high frequency switching topology with low DC-link voltage and switching losses contributing significantly to the overall power losses is presented providing new degrees of freedom for setting test conditions. The particularities of semiconductor power devices in power cycling tests are thematized in chapter 5. The first part describes standard packages and addressed failure mechanisms in power cycling. For all relevant power electronic devices in silicon and silicon carbide, the devices’ characteristics, methods for power cycling and their consequences for test results are explained. The work is concluded and suggestions for future work are given in chapter 6.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 257Diese Arbeit bereichert den Stand der Wissenschaft auf dem Gebiet von Lastwechseltests mit Beiträgen zu verbesserter Messgenauigkeit, vorgeschlagenen Teststandstopologien und verbesserten Teststrategien für verschiedene Arten von leistungselektronischen Bauelementen. Kurzgefasst der Methodik von Lastwechseltests. Das erste Themengebiet in Kapitel 1 und Kapitel 2 beschreibt den aktuellen Stand zu Lastwechseltests im Kontext von Design für Zuverlässigkeit, welcher in anzuwendenden Standards und publizierten Lebensdauermodellen dokumentiert ist. Messmethoden für relevante physikalische Parameter in Lastwechseltests sind in Kapitel 3. erläutert. Zunächst werden dynamische und statische Messgenauigkeit für Spannung, Strom und Temperaturen diskutiert. Die tatsächlich erreichbare Messverzögerung tMD der maximalen Sperrschichttemperatur Tjmax und deren Auswirkung auf die Messgenauigkeit der Lastwechselfestigkeit wird dargelegt. Danach werden Methoden zur Rückextrapolation zum Zeitpunkt des Abschaltvorgangs des Laststroms diskutiert. Schließlich wird die Charakterisierung des Wärmepfads vom Bauelement zur Wärmesenke mittels Messung der thermischen Impedanz Zth behandelt. In Kapitel 4 werden Teststandstopologien beginnend mit standardmäßig genutzten ein- und mehrsträngigen DC-Testständen vorgestellt. Drei vom Autor umgesetzte anwendungsnahe Topologien werden erklärt. Für Tests mit Thyristoren wird ein Testkonzept mit angeschnittenem sinusförmigem Strom und in situ Messung der Sperrschichttemperatur eingeführt. Eine umrichterähnliche Topologie mit aktiv schaltenden IGBTs wird vorgestellt. Zuletzt wird eine Topologie mit hoch frequent schaltenden Prüflingen an niedriger Gleichspannung bei der Schaltverluste signifikant zur Erwärmung der Prüflinge beitragen vorgestellt. Dies ermöglicht neue Freiheitsgrade um Testbedingungen zu wählen. Die Besonderheiten von leistungselektronischen Bauelementen werden in Kapitel 5 thematisiert. Der erste Teil beschreibt Gehäusetypen und adressierte Fehlermechanismen in Lastwechseltests. Für alle untersuchten Bauelementtypen in Silizium und Siliziumkarbid werden Charakteristiken, empfohlene Methoden für Lastwechseltests und Einflüsse auf Testergebnisse erklärt. Die Arbeit wird in Kapitel 6 zusammengefasst und Vorschläge zu künftigen Arbeiten werden unterbreitet.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 25

Analysis of performance of SiC bipolar semiconductor devices for grid-level converters

Recent commercialization of SiC bipolar devices, including SiC BJT, SiC MPS diode and SiC PiN diodes have enabled potential candidates to replace their SiC unipolar counterparts. However, the prospects of 4H-SiC power bipolar devices still need further investigation. This thesis compares the static and dynamic performance and reliability for the commercial SiC bipolar devices including SiC BJT, SiC MPS diode and SiC PiN diode and their similarly rated Silicon counterparts mainly by means of experimental measurements.Through comprehensive double-pulse measurements, the turn-on and turn-off transition in Silicon BJT is seen to be much slower than that of the SiC BJT while the transient time will increase with temperature and decreases with collector currents. The common-emitter current gain (β) of SiC BJT is also found to be much higher than its Silicon counterpart. Significant turn-off delay is observed in single Si BJT which becomes worse when in parallel connection as it aggravates the current mismatch across the two devices, while this delay is almost non-existent in SiC devices. The current collapse seen in single SiC BJT is mitigated by parallel connection. These are dependant on temperature and base resistance, especially in the case of Silicon BJT. The static performance of power Silicon and SiC BJT has also been evaluated. It has been found that the higher base-emitter junction voltage of SiC BJTs enables quasi-saturation mode of operation with low on-resistance, which is also the case for Silicon BJTs only at high base currents. In terms of DC gain measured under steady state operation, the observed negative temperature coefficient (NTC) of β in SiC BJTs and the positive coefficient (PTC) in Silicon BJTs can make the β of SiC BJT lower than that in Silicon at high temperatures. It has been found that parallel connection promotes both the on-state conductivity and current gain in Silicon BJTs and conductivity in SiC BJTs.The characterization of power diodes reveals that the superior switching performance of the SiC MPS & JBS diode when compared with the Si PiN diode is due to the absence of the stored charge. This also leads to the larger on-state voltage in both SiC diodes and becomes worse at high currents under high temperatures. Through comprehensive Unclamped Inductive Switching (UIS) measurements, it is seen that the avalanche ruggedness of SiC MPS & JBS diodes outperform that of the closely rated Silicon PiN diode taking advantage of the wide-bandgap properties of SiC. Higher critical avalanche energy and thus better avalanche ruggedness can also be observed in SiC JBS diode compared with the SiC MPS diode. SiC MPS diodes can compete with Si PiN diodes in terms of the surge current limits, while the SiC JBS diode failed under a lower electrothermal stress. This is observed by the dramatic increase in its reverse leakage current at lower voltages.The 15 kV SiC PiN diodes feature smaller device dimensions, less reverse recovery charge and less on-resistance when compared to the 15 kV Silicon PiN diodes. Nevertheless, when evaluating its long-term reliability by using the aggravated power cycling configuration, the high junction temperature together with the dislocation defects in the SiC PiN diode accelerate its degradation. Such degradations are not observed in Silicon PiN diodes for the same junction temperature and high-temperature stress periods

Health Condition Monitoring and Fault-Tolerant Operation of Adjustable Speed Drives

Adjustable speed drives (ASDs) have been extensively used in industrial applications over the past few decades because of their benefits of energy saving and control flexibilities. However, the wider penetration of ASD systems into industrial applications is hindered by the lack of health monitoring and fault-tolerant operation techniques, especially in safety-critical applications. In this dissertation, a comprehensive portfolio of health condition monitoring and fault-tolerant operation strategies is developed and implemented for multilevel neutral-point-clamped (NPC) power converters in ASDs. Simulations and experiments show that these techniques can improve power cycling lifetime of power transistors, on-line diagnosis of switch faults, and fault-tolerant capabilities.The first contribution of this dissertation is the development of a lifetime improvement Pulse Width Modulation (PWM) method which can significantly extend the power cycling lifetime of Insulated Gate Bipolar Transistors (IGBTs) in NPC inverters operating at low frequencies. This PWM method is achieved by injecting a zero-sequence signal with a frequency higher than that of the IGBT junction-to-case thermal time constants. This, in turn, lowers IGBT junction temperatures at low output frequencies. Thermal models, simulation and experimental verifications are carried out to confirm the effectiveness of this PWM method. As a second contribution of this dissertation, a novel on-line diagnostic method is developed for electronic switch faults in power converters. Targeted at three-level NPC converters, this diagnostic method can diagnose any IGBT faults by utilizing the information on the dc-bus neutral-point current and switching states. This diagnostic method only requires one additional current sensor for sensing the neutral-point current. Simulation and experimental results verified the efficacy of this diagnostic method.The third contribution consists of the development and implementation of a fault-tolerant topology for T-Type NPC power converters. In this fault-tolerant topology, one additional phase leg is added to the original T-Type NPC converter. In addition to providing a fault-tolerant solution to certain switch faults in the converter, this fault-tolerant topology can share the overload current with the original phase legs, thus increasing the overload capabilities of the power converters. A lab-scale 30-kVA ASD based on this proposed topology is implemented and the experimental results verified its benefits

Real-Time acoustic emission monitoring of wear-out failure in sic power electronic devices during power cycling tests

C. Choe, C. Chen, S. Nagao and K. Suganuma, "Real-Time Acoustic Emission Monitoring of Wear-Out Failure in SiC Power Electronic Devices During Power Cycling Tests," in IEEE Transactions on Power Electronics, vol. 36, no. 4, pp. 4420-4428, April 2021, doi: 10.1109/TPEL.2020.3024986

Development and characterisation of pressed packaging solutions for high-temperature high-reliability SiC power modules

SiC is a wide bandgap semiconductor with better electrothermal properties than silicon, including higher temperature of operation, higher breakdown voltage, lower losses and the ability to switch at higher frequencies. However, the power cycling performance of SiC devices in traditional silicon packaging systems is in need of further investigation since initial studies have shown reduced reliability. These traditional packaging systems have been developed for silicon, a semiconductor with different electrothermal and thermomechanical properties from SiC, hence the stresses on the different components of the package will change. Pressure packages, a packaging alternative where the weak elements of the traditional systems like wirebonds are removed, have demonstrated enhanced reliability for silicon devices however, there has not been much investigation on the performance of SiC devices in press-pack assemblies. This will be important for high power applications where reliability is critical. In this paper, SiC Schottky diodes in pressure packages have been evaluated, including the electrothermal characterisation for different clamping forces and contact materials, the thermal impedance evaluation and initial thermal cycling studies, focusing on the use of aluminium graphite as contact material

A Low Temperature Co-fired Ceramic (LTCC) Interposer Based Three-Dimensional Stacked Wire Bondless Power Module

The objective of this dissertation research is to develop a low temperature co-fired ceramic (LTCC) interposer-based module-level 3-D wire bondless stacked power module. As part of the dissertation work, the 3-D wire bondless stack is designed, simulated, fabricated and characterized. The 3-D wire bondless stack is realized with two stand-alone power modules in a half-bridge configuration. Each stand-alone power module consists of two 1200 V 25 A silicon insulated-gate bipolar transistor (IGBT) devices in parallel and two 1200 V 20 A Schottky barrier diodes (SBD) in an antiparallel configuration. A novel interconnection scheme with conductive clamps and a spring loaded LTCC interposer is introduced to establish electrical connection between the stand-alone power modules to connect them in series to realize a half-bridge stack. Process development to fabricate the LTCC based 3-D stack is performed. In traditional power modules, wire bonds are used as a top side interconnections that introduce additional parasitic inductance in the current conduction path and prone to failure mechanism under high thermomechanical stresses. The loop inductance of the proposed 3-D half-bridge module exhibits 71% lower parasitic inductance compared to a wire bonded module. The 3-D stack exhibits better switching performance compared to the wire bonded counterpart. The measurement results for the 3-D stack shows 30% decrease in current overshoot at turn-on and 43% voltage overshoot at turn-off compared to the wire bonded module. Through measurements, it has been shown that the conducted noise reduces by 20 dB in the frequency range 20-30 MHz for the 3-D stack compared to the wire bonded counterpart. A simulation methodology using co-simulation techniques using ANSYS EM software tools is developed to predict EMI of a power module. Hardware verification of the proposed simulation methodology is performed to validate the co-simulation technique. The correlation coefficient between the measurement and simulation is found to be 0.73. It is shown that 53% of the variability in the simulation can be explained by the simulated result. Moreover, the simulated and measured amplitudes of the EMI spectrum closely match with each other with some variations due to round-off errors due to the FFT conversion