Hybrid-Phase-Transition FET Devices for Logic Computation

Hybrid-phase-transition FETs (HyperFETs), built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON-to- OFF current ratio. In this article, we describe a comprehensive study carried out to explore the potential of these devices for low-power and energy-limited logic applications. HyperFETs with different ON-OFF current tradeoffs are evaluated at the circuit level. The results show limited improvement over conventional transistors in terms of power and energy. However, based on this analysis, this article proposes different design techniques to overcome the drawbacks identified in the study and thereby make better use of HyperFETs. Hybrid circuits, using both FinFETs and HyperFETs, and circuits combining different HyperFET devices are introduced and evaluated. At some frequencies, reductions of over 40% were obtained with respect to FinFET-only implementations, while minimum energy per operation values were obtained, which were lower than those achieved with low standby power (LSTP) FinFETs and high-performance (HP) FinFETs. This article also evaluates the impact of PTM transition time on the power performance of HyperFET circuits.Ministerio de Economía y Competitividad, FEDER TEC2017-87052-

A Novel Configuration of A Microstrip Power Amplifier based on GaAs-FET for ISM Applications

Power Amplifiers (PA) are very indispensable components in the design of numerous types of communication transmitters employed in microwave technology. The methodology is exemplified through the design of a 2.45GHz microwave power Amplifier (PA) for the industrial, scientific and medical (ISM) applications using microstrip technology. The main design target is to get a maximum power gain while simultaneously achieving a maximum output power through presenting the optimum impedance which is characteristically carried out per adding a matching circuit between the source and the input of the power amplifier and between the load and the output of the power amplifier. A "T" matching technique is used at the input and the output sides of transistor for assure in band desired that this circuit without reflections and to obtain a maximum power gain. The proposed power amplifier for microwave ISM applications is designed, simulated and optimized by employing Advanced Design System (ADS) software by Agilent. The PA shows good performances in terms of return loss, output power, power gain and stability; the circuit has an input return loss of -38dB and an output return loss of -33.5dB. The 1-dB compression point is 8.69dBm and power gain of the PA is 19.4dBm. The Rollet's Stability measure B1 and the stability factor K of the amplifier is greater than 0 and 1 respectively, which shows that the circuit is unconditionally stable. The total chip size of the PA is 73.5× 36 mm2

The 30/20 GHz flight experiment system, phase 2. Volume 1: Executive summary

Summary information on the final communication system design, communication payload, space vehicle, and development plan for the 30/20 GHz flight experiment will be installed on the LEASAT spacecraft which will be placed into orbit from the space shuttle cargo bay. The communication concept has two parts: a truck service and a customer premise service (CPS). The trucking system serves four spot beams which are interconnected in a satellite switched time division multiple access mode by an IF switch matrix. The CPS covers two large areas of the eastern United States with a pair of scanning beams

The 30/20 GHz flight experiment system, phase 2. Volume 2: Experiment system description

A detailed technical description of the 30/20 GHz flight experiment system is presented. The overall communication system is described with performance analyses, communication operations, and experiment plans. Hardware descriptions of the payload are given with the tradeoff studies that led to the final design. The spacecraft bus which carries the payload is discussed and its interface with the launch vehicle system is described. Finally, the hardwares and the operations of the terrestrial segment are presented

Highly Integrated Dc-dc Converters

A monolithically integrated smart rectifier has been presented first in this work. The smart rectifier, which integrates a power MOSFET, gate driver and control circuitry, operates in a self-synchronized fashion based on its drain-source voltage, and does not need external control input. The analysis, simulation, and design considerations are described in detail. A 5V, 5-µm CMOS process was used to fabricate the prototype. Experimental results show that the proposed rectifier functions as expected in the design. Since no dead-time control needs to be used to switch the sync-FET and ctrl-FET, it is expected that the body diode losses can be reduced substantially, compared to the conventional synchronous rectifier. The proposed self-synchronized rectifier (SSR) can be operated at high frequencies and maintains high efficiency over a wide load range. As an example of the smart rectifier\u27s application in isolated DC-DC converter, a synchronous flyback converter with SSR is analyzed, designed and tested. Experimental results show that the operating frequency could be as high as 4MHz and the efficiency could be improved by more than 10% compared to that when a hyper fast diode rectifier is used. Based on a new current-source gate driver scheme, an integrated gate driver for buck converter is also developed in this work by using a 0.35µm CMOS process with optional high voltage (50V) power MOSFET. The integrated gate driver consists both the current-source driver for high-side power MOSFET and low-power driver for low-side power iv MOSFET. Compared with the conventional gate driver circuit, the current-source gate driver can recovery some gate charging energy and reduce switching loss. So the current-source driver (CSD) can be used to improve the efficiency performance in high frequency power converters. This work also presents a new implementation of a power supply in package (PSiP) 5MHz buck converter, which is different from all the prior-of-art PSiP solutions by using a high-Q bondwire inductor. The high-Q bondwire inductor can be manufactured by applying ferrite epoxy to the common bondwire during standard IC packaging process, so the new implementation of PSiP is expected to be a cost-effective way of power supply integration

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET

Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially to the high-threshold voltage (VTH) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a non-ferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high-VTH state and thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low-VTH state stability. Comprehensive theoretical and experimental validation have been performed on fully-depleted silicon-on-insulator (FDSOI) FeFETs integrated on 22 nm platform, which intrinsically has dual ports with its buried oxide layer acting as the non-ferroelectric dielectric. Novel applications that can exploit the proposed dual-port FeFET are proposed and experimentally demonstrated for the first time, including FPGA that harnesses its read disturb-free feature and tunable analog electronics (e.g., frequency tunable ring oscillator in this work) leveraging the separated write and read paths.Comment: 32 page