A FRACTIONAL DELAY FIR FILTER BASED ON LAGRANGE INTERPOLATION OF FARROW STRUCTURE

An efficient implementation technique for the Lagrange interpolation is derived. This formulation called the Farrow structure leads to a version of Lagrange interpolation that is well suited to time varying FD filtering. Lagrange interpolation is mostly used for fractional delay approximation as it can be used for increasing the sampling rate of signals and systems. Lagrange interpolation is one of the representatives for a class of polynomial interpolation techniques. The computational cost of this structure is reduced as the number of multiplications are minimised in the new structure when compared with the conventional structure

Maximally flat and least-square co-design of variable fractional delay filters for wideband software-defined radio

This paper describes improvements in a Farrow-structured variable fractional delay (FD) Lagrange filter for all-pass FD interpolation. The main idea is to integrate the truncated sinc into the Farrow structure of a Lagrange filter, in order that a superior FD approximation in the least-square sense can be achieved. Its primary advantages are the lower level of mean-square-error (MSE) over the whole FD range and the reduced implementation cost. Extra design parameters are introduced for making the trade-off between MSE and maximal flatness under different design requirements. Design examples are included, illustrating an MSE reduction of 50% compared to a classical Farrow-structured Lagrange interpolator while the implementation cost is reduced. This improved variable FD interpolation system is suitable for many applications, such as sample rate conversion, digital beamforming and timing synchronization in wideband software-defined radio (SDR) communications

Signal processing with frequency and phase shift keying modulation in telecommunications

In this paper represents research improving effectiveness of signal processing in telecommunication devices especially for its part, which relates to providing its noise resistance in conditions of noise and interference. This objective has been achieved through development of methods and means for optimization of filtering devices and semigraphical interpretation of clock synchronization systems in telecommunications with frequency shift keying on the base of stochastic models what determines relevance of the subject. Separately, in an article considered the urgent task is using of modified synchronization methods based on the interference influence of adjacent symbols on the phase criterion tract, in particular the use of the modified synchronization scheme, in order to get a formalized outlook representation of the synchronization schemas based on the polyphase structures with using a bank of filters, that allows to improve the characteristics of digital telecommunication channels. This work is devoted to the examination and modeling of these ways. The proposed ideas and results for the construction of synchronization systems can be used in modern means of telecommunication

Envelope and phase delays correction in an EER radio architecture

International audienceThis article deals with synchronization in the Envelope Elimination and Restoration (EER) type of transmitter architecture. To illustrate the performances of such solution, we choose to apply this architecture to a 64 carriers 16QAM modulated OFDM. We first introduce the problematic of the realisation of a highly linear transmitter.We then present the Envelope Elimination and Restoration solution and draw attention to its major weakness: a high sensitivity to desynchronization between the phase and envelope signal paths. To address this issue, we propose an adaptive synchronization algorithm relying on a feedback loop, a LeastMean Square formulation and involving an interpolation step. It enables the correction of delay mismatches and tracking of possible variations. We demonstrate that the quality of the interpolator has a direct impact on Error Vector Magnitude (EVM) value and output spectrum. Implementation details are provided along with an analysis of the behaviour and performances of the method. We present HPADS and Matlab simulation results and then focus on the enhancement of the transmitter performances using the proposed algorithm

Maximum-likelihood estimation of delta-domain model parameters from noisy output signals

Fast sampling is desirable to describe signal transmission through wide-bandwidth systems. The delta-operator provides an ideal discrete-time modeling description for such fast-sampled systems. However, the estimation of delta-domain model parameters is usually biased by directly applying the delta-transformations to a sampled signal corrupted by additive measurement noise. This problem is solved here by expectation-maximization, where the delta-transformations of the true signal are estimated and then used to obtain the model parameters. The method is demonstrated on a numerical example to improve on the accuracy of using a shift operator approach when the sample rate is fast

The design and multiplier-less realization of software radio receivers with reduced system delay

This paper studies the design and multiplier-less realization of a new software radio receiver (SRR) with reduced system delay. It employs low-delay finite-impulse response (FIR) and digital allpass filters to effectively reduce the system delay of the multistage decimators in SRRs. The optimal least-square and minimax designs of these low-delay FIR and allpass-based filters are formulated as a semidefinite programming (SDP) problem, which allows zero magnitude constraint at ω = π to be incorporated readily as additional linear matrix inequalities (LMIs). By implementing the sampling rate converter (SRC) using a variable digital filter (VDF) immediately after the integer decimators, the needs for an expensive programmable FIR filter in the traditional SRR is avoided. A new method for the optimal minimax design of this VDF-based SRC using SDP is also proposed and compared with traditional weight least squares method. Other implementation issues including the multiplier-less and digital signal processor (DSP) realizations of the SRR and the generation of the clock signal in the SRC are also studied. Design results show that the system delay and implementation complexities (especially in terms of high-speed variable multipliers) of the proposed architecture are considerably reduced as compared with conventional approaches. © 2004 IEEE.published_or_final_versio

Fractional Order and Virtual Variable Sampling Design of Repetitive Control for Power Converters

With the growth of electricity demand and renewable energy power source, power converter becomes a more and more significant component in electrical power systems. The requirement of the power converter controller is to produce an accurate and low-distorted voltage or current under different load conditions. Although the conventional controller can meet the requirement of some applications, it requires accurate knowledge of the system model and cannot provide a satisfactory result especially under nonlinear loads or sudden load change. Repetitive control (RC) presents an attractive solution to achieve excellent steady-state tracking error and low total harmonic distortion for periodic signals, and it is increasingly applied to power converter systems. However, there are still some limitations or requirements of RC when it is applied to power electronics system: first, RC requires the system sampling frequency is a fixed value and needs to be an integral multiple of the reference frequency; second, low controller sampling frequency results in low phase lead compensation resolution in RC, which leads to control inaccuracy; third, conventional RC does not have frequency adaptability to reference frequency fluctuation, and even a small reference frequency fluctuation can lead to severe performance degradation. To overcome the conventional RC limitations, two advanced design methods are proposed in the thesis: fractional order delay and virtual variable sampling. The method of fractional order delay approximates the non-integer delay part by building a finite impulse response filter. This improved method is not only able to be applied on a period delay unit but also on phase-lead compensation. The accurate period delay and phase lead compensation show a noticeable improvement in RC performance. Although fractional order delay can meet the requirement on most of the applications, it also has a minimal adjustable range on the reference frequency. To achieve an essential solution to this problem, the virtual variable sampling (VVS) method is developed. The VVS approximates a variable sampling unit instead of the fixed system unit for RC and its filters, in which RC is able to be frequency adaptive. Comparing with the method of fractional order delay, the VVS method can provide a much more extensive adjustable range on the reference frequency. Based on the system performance under the conventional controller, power converter always has uneven distortion distribution. To further improve the stability and eliminate harmonic distortions efficiently, two selective harmonic RC schemes are introduced - nk ± m order harmonic RC and DFT-based selective harmonic RC. However, these selective RC schemes also suffer from the particular requirement of system sampling frequency and low reference frequency adaptability. Applying VVS methods on these two schemes can effectively present an improvement on their frequency adaptability. To verify the proposed methods’ effectiveness, a complete series of power electronics applications are carried out. These applications include single-phase and three-phase DC/AC power converter, single-phase AC/DC power converter, and single-phase grid-connected power converter. The detailed system modeling and the proposed RC schemes are presented for each power electronics application