(1) time Parallel Agorithm for Finding 2D Convex Hull on a Reconfigurable Mesh Computer Architecture

In this paper we propose a parallel algorithm in image processing in (1) time, intended for a parallel machine '' Reconfigurable Mesh Computer (RMC), of size n x n Elementary Processors (PE). The algorithm consists in determining the convex envelope of a two-level 2D image with a complexity in (1) time. The approach used is purely geometric. It is based solely on the projection of the coordinates of PEs retained in specific quadrants and on the application of the algorithm that determines the Min / Max in (1) time. This has reduced the complexity of the algorithm for determining the convex hull at (1) time

Architectures parallèles spécialisées pour le traitement d'image

Un domaine d'applications comme le traitement d'image requiert une telle puissance de calcul que seules les architectures parallèles spécialisées "taillées sur mesure" peuvent satisfaire les contraintes de vitesse, de performance et d'encombrement. La réalisation d'architectures parallèles spécialiseés pour l'image est abordée de différentes facons. Dans la catégorie des machines SIMD, on note les réseaux bidimensionnels à base de processeurs bit-serie (MPP, GAPP, DAP) les réseaux linéaires réalises à partir de processeurs plus performants (16 voire 32 bits), (CLIP7, SLAP, SYMPATI, PRINCETON). Parmi les machines MIMD, on note essentiellement les machines WARP, iWARP et les approches à base de processeurs de traitement de signal (DSP) supportant ainsi différents types de parallélisme (systolique, pipeline,- ...). Aussi les approches employées à ce jour sont variées et leur comparaison difficile. L'objectif de cet article est de proposer un panorama des architectures parallèles spécialisées pour l'image jugeés les plus significatives. Pour chacune des réalisations décrites, l'accent est mis sur l'aspect qui présente le plus d'intérêt (structure du processeur, organisation de la machine, mode de fonctionnement, système d'interconnexion)

Embeddings Among Toruses and Meshes

Toruses and meshes include graphs of many varieties of topologies, with lines, rings, and hypercubes being special cases. Given a d-dimensional torus or mesh G and a c-dimensional torus or mesh H of the same size, we study the problem of embedding G in H to minimize the dilation cost. For increasing dimension cases (d \u3c c) in which the shapes of G and H satisfy the condition of expansion, the dilation costs of our embeddings are either 1 or 2, depending on the types of graphs of G and H. These embeddings a,re optimal except when G is a torus of even size and H is a mesh. For lowering dimension cases (d \u3e c) in which the shapes of G and H satisfy the condition of reduction, the dilation costs of our embeddings depend on the shapes of G and H. These embeddings, however, are not optimal in general. For the special cases in which G and H are square, the embedding results above can always be used to construct embeddings of G in H: these embeddings are all optimal for increasing dimension cases in which the dimension of H is divisible by the dimension of G, and all optimal to within a constant for fixed values of d and c for lowering dimension cases. Our main analysis technique is based on a generalization of Gray code for radix-2 (binary) numbering system to similar sequences for mixed-radix numbering systems

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

Visual inspection : image sampling, algorithms and architectures

The thesis concerns the hexagonal sampling of images, the processing of industrially derived images, and the design of a novel processor element that can be assembled into pipelines to effect fast, economic and reliable processing. A hexagonally sampled two dimensional image can require 13.4% fewer sampling points than a square sampled equivalent. The grid symmetry results in simpler processing operators that compute more efficiently than square grid operators. Computation savings approaching 44% arc demonstrated. New hexagonal operators arc reported including a Gaussian smoothing filter, a binary thinner, and an edge detector with comparable accuracy to that of the Sobel detector. The design of hexagonal arrays of sensors is considered. Operators requiring small local areas of support are shown to be sufficient for processing controlled lighting and industrial images. Case studies show that small features in hexagonally processed images maintain their shape better, and that processes can tolerate a lower signal to noise ratio, than that for equivalent square processed images. The modelling of small defects in surfaces has been studied in depth. The flexible programmable processor element can perform the low level local operators required for industrial image processing on both square and hexagonal grids. The element has been specified and simulated by a high level computer program. A fast communication channel allows for dynamic reprogramming by a control computer, and the video rate element can be assembled into various pipeline architectures, that may eventually be adaptively controlled