54 research outputs found
STT-MRAM characterization and its test implications
Spin torque transfer (STT)-magnetoresistive random-access memory (MRAM) has come
a long way in research to meet the speed and power consumption requirements for future
memory applications. The state-of-the-art STT-MRAM bit-cells employ magnetic tunnel
junction (MTJ) with perpendicular magnetic anisotropy (PMA). The process repeatabil-
ity and yield stability for wafer fabrication are some of the critical issues encountered in
STT-MRAM mass production. Some of the yield improvement techniques to combat the
e ect of process variations have been previously explored. However, little research has been
done on defect oriented testing of STT-MRAM arrays. In this thesis, the author investi-
gates the parameter deviation and non-idealities encountered during the development of
a novel MTJ stack con guration. The characterization result provides motivation for the
development of the design for testability (DFT) scheme that can help test and characterize
STT-MRAM bit-cells and the CMOS peripheral circuitry e ciently.
The primary factors for wafer yield degradation are the device parameter variation and
its non-uniformity across the wafer due to the fabrication process non-idealities. There-
fore, e ective in-process testing strategies for exploring and verifying the impact of the
parameter variation on the wafer yield will be needed to achieve fabrication process opti-
mization. While yield depends on the CMOS process variability, quality of the deposited
MTJ lm, and other process non-idealities, test platform can enable parametric optimiza-
tion and veri cation using the CMOS-based DFT circuits. In this work, we develop a DFT
algorithm and implement a DFT circuit for parametric testing and prequali cation of the
critical circuits in the CMOS wafer. The DFT circuit successfully replicates the electrical
characteristics of MTJ devices and captures their spatial variation across the wafer with
an error of less than 4%. We estimate the yield of the read sensing path by implement-
ing the DFT circuit, which can replicate the resistance-area product variation up to 50%
from its nominal value. The yield data from the read sensing path at di erent wafer loca-
tions are analyzed, and a usable wafer radius has been estimated. Our DFT scheme can
provide quantitative feedback based on in-die measurement, enabling fabrication process
optimization through iterative estimation and veri cation of the calibrated parameters.
Another concern that prevents mass production of STT-MRAM arrays is the defect
formation in MTJ devices due to aging. Identifying manufacturing defects in the magnetic
tunnel junction (MTJ) device is crucial for the yield and reliability of spin-torque-transfer
(STT) magnetic random-access memory (MRAM) arrays. Several of the MTJ defects result
in parametric deviations of the device that deteriorate over time. We extend our work on
the DFT scheme by monitoring the electrical parameter deviations occurring due to the
defect formation over time. A programmable DFT scheme was implemented for a sub-arrayin 65 nm CMOS technology to evaluate the feasibility of the test scheme. The scheme utilizes the read sense path to compare the bit-cell electrical parameters against known
DFT cells characteristics. Built-in-self-test (BIST) methodology is utilized to trigger the
onset of the fault once the device parameter crosses a threshold value. We demonstrate
the operation and evaluate the accuracy of detection with the proposed scheme. The
DFT scheme can be exploited for monitoring aging defects, modeling their behavior and
optimization of the fabrication process.
DFT scheme could potentially nd numerous applications for parametric characteriza-
tion and fault monitoring of STT-MRAM bit-cell arrays during mass production. Some of
the applications include a) Fabrication process feedback to improve wafer turnaround time,
b) STT-MRAM bit-cell health monitoring, c) Decoupled characterization of the CMOS pe-
ripheral circuitry such as read-sensing path and sense ampli er characterization within the
STT-MRAM array. Additionally, the DFT scheme has potential applications for detec-
tion of fault formation that could be utilized for deploying redundancy schemes, providing
a graceful degradation in MTJ-based bit-cell array due to aging of the device, and also
providing feedback to improve the fabrication process and yield learning
Error Characterization and Correction Techniques for Reliable STT-RAM Designs
The concerns on the continuous scaling of mainstream memory technologies have motivated tremendous investment to emerging memories. Being a promising candidate, spin-transfer torque random access memory (STT-RAM) offers nanosecond access time comparable to SRAM, high integration density close to DRAM, non-volatility as Flash memory, and good scalability. It is well positioned as the replacement of SRAM and DRAM for on-chip cache and main memory applications. However, reliability issue continues being one of the major challenges in STT-RAM memory designs due to the process variations and unique thermal fluctuations, i.e., the stochastic resistance switching property of magnetic devices.
In this dissertation, I decoupled the reliability issues as following three-folds: First, the characterization of STT-RAM operation errors often require expensive Monte-Carlo runs with hybrid magnetic-CMOS simulation steps, making it impracticable for architects and system designs; Second, the state of the art does not have sufficiently understanding on the unique reliability issue of STT-RAM, and conventional error correction codes (ECCs) cannot efficiently handle such errors; Third, while the information density of STT-RAM can be boosted by multi-level cell (MLC) design, the more prominent reliability concerns and the complicated access mechanism greatly limit its applications in memory subsystems.
Thus, I present a novel through solution set to both characterize and tackle the above reliability challenges in STT-RAM designs. In the first part of the dissertation, I introduce a new characterization method that can accurately and efficiently capture the multi-variable design metrics of STT-RAM cells; Second, a novel ECC scheme, namely, content-dependent ECC (CD-ECC), is developed to combat the characterized asymmetric errors of STT-RAM at 0->1 and 1->0 bit flipping's; Third, I present a circuit-architecture design, namely state-restricted multi-level cell (SR-MLC) STT-RAM design, which simultaneously achieves high information density, good storage reliability and fast write speed, making MLC STT-RAM accessible for system designers under current technology node. Finally, I conclude that efficient robust (or ECC) designs for STT-RAM require a deep holistic understanding on three different levels-device, circuit and architecture. Innovative ECC schemes and their architectural applications, still deserve serious research and investigation in the near future
Developing Variation Aware Simulation Tools, Models, and Designs for STT-RAM
DEVELOPING VARIATION AWARE SIMULATION TOOLS, MODELS, AND DESIGNS
FOR STT-RAM
Enes Eken, PhD
University of Pittsburgh, 2017
In recent years, we have been witnessing the rise of spin-transfer torque random access memory
(STT-RAM) technology. There are a couple of reasons which explain why STT-RAM has attracted
a great deal of attention. Although conventional memory technologies like SRAM, DRAM
and Flash memories are commonly used in the modern computer industry, they have major shortcomings,
such as high leakage current, high power consumption and volatility. Although these
drawbacks could have been overlooked in the past, they have become major concerns. Its characteristics,
including low-power consumption, fast read-write access time and non-volatility make
STT-RAM a promising candidate to solve the problems of other memory technologies. However,
like all other memory technologies, STT-RAM has some problems such as long switching time and
large programming energy of Magnetic Tunneling Junction (MTJ) which are waiting to be solved.
In order to solve these long switching time and large programming energy problems, Spin-Hall
Effect (SHE) assisted STT-RAM structure (SHE-RAM) has been recently invented. In this work, I
propose two possible SHE-RAM designs from the aspects of two different write access operations,
namely, High Density SHE-RAM and Disturbance Free SHE-RAM, respectively. In addition to
the SHE-RAM designs, I will also propose a simulation tool for STT-RAMs. As an early-stage
modeling tool, NVSim has been widely adopted for simulations of emerging nonvolatile memory
technologies in computer architecture research, including STT-RAM, ReRAM, PCM, etc. I will
introduce a new member of NVSim family – NVSim-VXs, which enables statistical simulation of
STT-RAM for write performance, errors, and energy consumption
Gestión de jerarquÃas de memoria hÃbridas a nivel de sistema
Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadoras y Automática y de Ku Leuven, Arenberg Doctoral School, Faculty of Engineering Science, leÃda el 11/05/2017.In electronics and computer science, the term ‘memory’ generally refers to devices that are used to store information that we use in various appliances ranging from our PCs to all hand-held devices, smart appliances etc. Primary/main memory is used for storage systems that function at a high speed (i.e. RAM). The primary memory is often associated with addressable semiconductor memory, i.e. integrated circuits consisting of silicon-based transistors, used for example as primary memory but also other purposes in computers and other digital electronic devices. The secondary/auxiliary memory, in comparison provides program and data storage that is slower to access but offers larger capacity. Examples include external hard drives, portable flash drives, CDs, and DVDs. These devices and media must be either plugged in or inserted into a computer in order to be accessed by the system. Since secondary storage technology is not always connected to the computer, it is commonly used for backing up data. The term storage is often used to describe secondary memory. Secondary memory stores a large amount of data at lesser cost per byte than primary memory; this makes secondary storage about two orders of magnitude less expensive than primary storage. There are two main types of semiconductor memory: volatile and nonvolatile. Examples of non-volatile memory are ‘Flash’ memory (sometimes used as secondary, sometimes primary computer memory) and ROM/PROM/EPROM/EEPROM memory (used for firmware such as boot programs). Examples of volatile memory are primary memory (typically dynamic RAM, DRAM), and fast CPU cache memory (typically static RAM, SRAM, which is fast but energy-consuming and offer lower memory capacity per are a unit than DRAM). Non-volatile memory technologies in Si-based electronics date back to the 1990s. Flash memory is widely used in consumer electronic products such as cellphones and music players and NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. The rapid increase of leakage currents in Silicon CMOS transistors with scaling poses a big challenge for the integration of SRAM memories. There is also the case of susceptibility to read/write failure with low power schemes. As a result of this, over the past decade, there has been an extensive pooling of time, resources and effort towards developing emerging memory technologies like Resistive RAM (ReRAM/RRAM), STT-MRAM, Domain Wall Memory and Phase Change Memory(PRAM). Emerging non-volatile memory technologies promise new memories to store more data at less cost than the expensive-to build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. These new memory technologies combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the non-volatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. The research and information on these Non-Volatile Memory (NVM) technologies has matured over the last decade. These NVMs are now being explored thoroughly nowadays as viable replacements for conventional SRAM based memories even for the higher levels of the memory hierarchy. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional(3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years...En el campo de la informática, el término ‘memoria’ se refiere generalmente a dispositivos que son usados para almacenar información que posteriormente será usada en diversos dispositivos, desde computadoras personales (PC), móviles, dispositivos inteligentes, etc. La memoria principal del sistema se utiliza para almacenar los datos e instrucciones de los procesos que se encuentre en ejecución, por lo que se requiere que funcionen a alta velocidad (por ejemplo, DRAM). La memoria principal está implementada habitualmente mediante memorias semiconductoras direccionables, siendo DRAM y SRAM los principales exponentes. Por otro lado, la memoria auxiliar o secundaria proporciona almacenaje(para ficheros, por ejemplo); es más lenta pero ofrece una mayor capacidad. Ejemplos tÃpicos de memoria secundaria son discos duros, memorias flash portables, CDs y DVDs. Debido a que estos dispositivos no necesitan estar conectados a la computadora de forma permanente, son muy utilizados para almacenar copias de seguridad. La memoria secundaria almacena una gran cantidad de datos aun coste menor por bit que la memoria principal, siendo habitualmente dos órdenes de magnitud más barata que la memoria primaria. Existen dos tipos de memorias de tipo semiconductor: volátiles y no volátiles. Ejemplos de memorias no volátiles son las memorias Flash (algunas veces usadas como memoria secundaria y otras veces como memoria principal) y memorias ROM/PROM/EPROM/EEPROM (usadas para firmware como programas de arranque). Ejemplos de memoria volátil son las memorias DRAM (RAM dinámica), actualmente la opción predominante a la hora de implementar la memoria principal, y las memorias SRAM (RAM estática) más rápida y costosa, utilizada para los diferentes niveles de cache. Las tecnologÃas de memorias no volátiles basadas en electrónica de silicio se remontan a la década de1990. Una variante de memoria de almacenaje por carga denominada como memoria Flash es mundialmente usada en productos electrónicos de consumo como telefonÃa móvil y reproductores de música mientras NAND Flash solid state disks(SSDs) están progresivamente desplazando a los dispositivos de disco duro como principal unidad de almacenamiento en computadoras portátiles, de escritorio e incluso en centros de datos. En la actualidad, hay varios factores que amenazan la actual predominancia de memorias semiconductoras basadas en cargas (capacitivas). Por un lado, se está alcanzando el lÃmite de integración de las memorias Flash, lo que compromete su escalado en el medio plazo. Por otra parte, el fuerte incremento de las corrientes de fuga de los transistores de silicio CMOS actuales, supone un enorme desafÃo para la integración de memorias SRAM. Asimismo, estas memorias son cada vez más susceptibles a fallos de lectura/escritura en diseños de bajo consumo. Como resultado de estos problemas, que se agravan con cada nueva generación tecnológica, en los últimos años se han intensificado los esfuerzos para desarrollar nuevas tecnologÃas que reemplacen o al menos complementen a las actuales. Los transistores de efecto campo eléctrico ferroso (FeFET en sus siglas en inglés) se consideran una de las alternativas más prometedores para sustituir tanto a Flash (por su mayor densidad) como a DRAM (por su mayor velocidad), pero aún está en una fase muy inicial de su desarrollo. Hay otras tecnologÃas algo más maduras, en el ámbito de las memorias RAM resistivas, entre las que cabe destacar ReRAM (o RRAM), STT-RAM, Domain Wall Memory y Phase Change Memory (PRAM)...Depto. de Arquitectura de Computadores y AutomáticaFac. de InformáticaTRUEunpu
High-Performance Energy-Efficient and Reliable Design of Spin-Transfer Torque Magnetic Memory
In this dissertation new computing paradigms, architectures and design philosophy are proposed and evaluated for adopting the STT-MRAM technology as highly reliable, energy efficient and fast memory. For this purpose, a novel cross-layer framework from the cell-level all the way up to the system- and application-level has been developed. In these framework, the reliability issues are modeled accurately with appropriate fault models at different abstraction levels in order to analyze the overall failure rates of the entire memory and its Mean Time To Failure (MTTF) along with considering the temperature and process variation effects. Design-time, compile-time and run-time solutions have been provided to address the challenges associated with STT-MRAM. The effectiveness of the proposed solutions is demonstrated in extensive experiments that show significant improvements in comparison to state-of-the-art solutions, i.e. lower-power, higher-performance and more reliable STT-MRAM design
Magnetic and Spin Devices
As the scaling of electronic semiconductor devices displays signs of saturation, the main focus of research in microelectronics is shifting towards finding new computing paradigms. Electron spin offers additional functionality to digital charge-based devices. Several fundamental problems, including spin injection to a semiconductor, spin propagation and relaxation, and spin manipulation by the gate voltage, have been successfully resolved to open a path towards spin-based reprogrammable electron switches. Devices employing electron spin are nonvolatile; they are able to preserve the stored information without external power. Emerging nonvolatile devices are electrically addressable, possess a simple structure, and offer endurance and speed superior to flash memory. Having nonvolatile memory very close to CMOS offers a prospect of data processing in the nonvolatile segment, where the same devices are used to store and process the information. This opens perspectives for conceptually new low-power computing paradigms within Artificial Intelligence of Things (AIoT). This Special Issue focuses on all topics related to spintronic devices such as spin-based switches, magnetoresistive memories, energy harvesting devices, and sensors that can be employed in in-memory computing concepts and in Artificial Intelligence
Nanoscale Nonvolatile Memory Circuit Design using Emerging Spin Transfer Torque Magnetic Random Access Memory
Title from PDF of title page, viewed August 25, 2017Thesis advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 67-71)Thesis (M.S.)--School of Computing and Engineering. University of Missouri--Kansas City, 2016The spin transfer torque magnetic random access memory (STT-MRAM) is suitable for
embedded and second level cache memories in the mobile CPUs. STT-MRAM is a highly
potential nonvolatile memory (NVM) technology. There has been a growing demand to improve
the efficiency and reliability of the NVM circuits and architectures. we present a modified STT
MRAM cell design, where each cell is comprised of one magnetic tunneling junction (MTJ)
device and a regular access transistor. We provide analysis of device, circuit and memory
architecture level issues of STT-MRAM. The Modified 1M1T STT-MRAM bit cell circuit
offers simpler and more area- and power- efficient design compared to the existing STT-MRAM
cell design. Some device-circuit co-design issues are investigated to demonstrate ways to reduce
delay in MRAM circuits based on MTJ. An 8x8 conventional MRAM array is implemented
using the existing 2M2T cell and the Modified 1M1T cell to perform a comparative analysis at
the architecture level. The non-volatile nature of the proposed STT-MRAM is verified through
SPICE simulation. The circuit implementations and simulations are performed for 45nm
technology node.
As the transistor scales down it is prone to subthreshold leakage, gate-dielectric leakage,
Short channel effect and drain induced barrier lowering. Now alternative of Access transistor is
needed. We are using FinFET as access transistor in the STT-MRAM bit cell. FinFET based bit
cell is designed to get an advantage of scaling down. Analysis is done and proven that the power
consumption, standalone leakage current is less when compared to NMOS based STT-MRAM
bit cell. Also determined FinFET based bit cell produces less access time to access the logic
value from MTJ.
Now, Industry is looking to have computational and storage capability together and that can
be achieved through STT-MRAM. Addition to that there is a possibility to reduce power
consumption and leakage more. So replacing FinFET technology with Carbon Nano Tube Field
Effect Transistor (CNTFET) is required. As the conventional STT-MRAM requires certain
current to reverse the magnetization of MTJ and one CNTFET alone cannot produce sufficient
current required to store the logic value into MTJ. So new Bit cell is proposed using 3 CNTFET
and 1 MTJ, this bit cell is capable of storing 3 logic values at a time that is capable of doing
computation and act as AND gate. Also it utilizes less power to be in active region.
Sensing of any memory system is one of the main challenge in industry to get better
performance with less resources. Conventional Sense Amplifier (SA) used to sense the value
from SRAM, DRAM memory system is also used to sense the STT-MRAM memory. But use
of conventional SA is prone to some error. Modified Sense Amplifier is designed to overcome
the error produced from the conventional SA. It is compared with all the existing SA to get the
performance details of the modified SA.Introduction -- Planar NMOS based STT-MRAM bit cell analysis and circuit designing -- Performance improvement using FINFET based STT-MRAM circuit design -- Logic-in-memory using CNT-FET based STT-MRAM bit cell and optimization -- Error free sense amplifier design for STT-MRAM nonvolatile memor
Embedding Logic and Non-volatile Devices in CMOS Digital Circuits for Improving Energy Efficiency
abstract: Static CMOS logic has remained the dominant design style of digital systems for
more than four decades due to its robustness and near zero standby current. Static
CMOS logic circuits consist of a network of combinational logic cells and clocked sequential
elements, such as latches and flip-flops that are used for sequencing computations
over time. The majority of the digital design techniques to reduce power, area, and
leakage over the past four decades have focused almost entirely on optimizing the
combinational logic. This work explores alternate architectures for the flip-flops for
improving the overall circuit performance, power and area. It consists of three main
sections.
First, is the design of a multi-input configurable flip-flop structure with embedded
logic. A conventional D-type flip-flop may be viewed as realizing an identity function,
in which the output is simply the value of the input sampled at the clock edge. In
contrast, the proposed multi-input flip-flop, named PNAND, can be configured to
realize one of a family of Boolean functions called threshold functions. In essence,
the PNAND is a circuit implementation of the well-known binary perceptron. Unlike
other reconfigurable circuits, a PNAND can be configured by simply changing the
assignment of signals to its inputs. Using a standard cell library of such gates, a technology
mapping algorithm can be applied to transform a given netlist into one with
an optimal mixture of conventional logic gates and threshold gates. This approach
was used to fabricate a 32-bit Wallace Tree multiplier and a 32-bit booth multiplier
in 65nm LP technology. Simulation and chip measurements show more than 30%
improvement in dynamic power and more than 20% reduction in core area.
The functional yield of the PNAND reduces with geometry and voltage scaling.
The second part of this research investigates the use of two mechanisms to improve
the robustness of the PNAND circuit architecture. One is the use of forward and reverse body biases to change the device threshold and the other is the use of RRAM
devices for low voltage operation.
The third part of this research focused on the design of flip-flops with non-volatile
storage. Spin-transfer torque magnetic tunnel junctions (STT-MTJ) are integrated
with both conventional D-flipflop and the PNAND circuits to implement non-volatile
logic (NVL). These non-volatile storage enhanced flip-flops are able to save the state of
system locally when a power interruption occurs. However, manufacturing variations
in the STT-MTJs and in the CMOS transistors significantly reduce the yield, leading
to an overly pessimistic design and consequently, higher energy consumption. A
detailed analysis of the design trade-offs in the driver circuitry for performing backup
and restore, and a novel method to design the energy optimal driver for a given yield is
presented. Efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented,
in which the backup time is determined on a per-chip basis, resulting in minimizing
the energy wastage and satisfying the yield constraint. To achieve a yield of 98%,
the conventional approach would have to expend nearly 5X more energy than the
minimum required, whereas the proposed tunable approach expends only 26% more
energy than the minimum. A non-volatile threshold gate architecture NV-TLFF are
designed with the same backup and restore circuitry in 65nm technology. The embedded
logic in NV-TLFF compensates performance overhead of NVL. This leads to the
possibility of zero-overhead non-volatile datapath circuits. An 8-bit multiply-and-
accumulate (MAC) unit is designed to demonstrate the performance benefits of the
proposed architecture. Based on the results of HSPICE simulations, the MAC circuit
with the proposed NV-TLFF cells is shown to consume at least 20% less power and
area as compared to the circuit designed with conventional DFFs, without sacrificing
any performance.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201
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