Design of a Hybrid Modular Switch

Network Function Virtualization (NFV) shed new light for the design, deployment, and management of cloud networks. Many network functions such as firewalls, load balancers, and intrusion detection systems can be virtualized by servers. However, network operators often have to sacrifice programmability in order to achieve high throughput, especially at networks' edge where complex network functions are required. Here, we design, implement, and evaluate Hybrid Modular Switch (HyMoS). The hybrid hardware/software switch is designed to meet requirements for modern-day NFV applications in providing high-throughput, with a high degree of programmability. HyMoS utilizes P4-compatible Network Interface Cards (NICs), PCI Express interface and CPU to act as line cards, switch fabric, and fabric controller respectively. In our implementation of HyMos, PCI Express interface is turned into a non-blocking switch fabric with a throughput of hundreds of Gigabits per second. Compared to existing NFV infrastructure, HyMoS offers modularity in hardware and software as well as a higher degree of programmability by supporting a superset of P4 language

PCI Express Over Optical Links for Data Acquisition and Control

PCI Express is a new I/O technology for desktop, mobile, server and communications platforms designed to allow increasing levels of computer system performance. The serial nature of its links and the packet based protocols allows an easy geographical decoupling of a peripheral device. We have investigated the possibility of using an optical physical layer for the PCI Express, and we have built a bus adapter which can bridge remote busses (> 100m) to a single host computer without even the need of a specialized driver, given the legacy PCI compatibility of the PCI Express hardware. This adapter has been made tolerant to harsh environmental conditions, like strong magnetic fields or radiation fluxes, as the data acquisition needs of high energy physics experiments often require

Creating a PCI express interconnect in the gem5 simulator

In this thesis, the objective was to implement a PCI (Peripheral Component Interconnect) Express interconnect in the gem5 architecture simulator. The interconnect was designed with the goal of aiding accurate modeling of PCI Express-based devices in gem5 in the future. The PCI Express interconnect that was created consisted of a root complex, PCI Express switch, as well as individual PCI Express links. Each of these created components can work independently, and can be easily integrated into the existing gem5 platforms for the ARM Instruction Set Architecture. The created PCI Express interconnect was evaluated against a real PCI Express interconnect present on an Intel Xeon server platform. The bandwidth offered by both interconnects was compared by reading data from storage devices using the Linux utility “dd”. The results indicate that the gem5 PCI Express interconnect can provide between 81% - 91.6% of the bandwidth of the real PCI Express interconnect. However, architectural differences between the gem5 and Intel Xeon platforms used, as well as unimplemented features of the PCI Express protocol in the gem5 PCI Express interconnect, necessitate more strenuous validation of the created PCI Express interconnect before reaching a definitive conclusion on its performance

Exploitation from Malicious PCI Express Peripherals

The thesis of this dissertation is that, despite widespread belief in the security community, systems are still vulnerable to attacks from malicious peripherals delivered over the PCI Express (PCIe) protocol. Malicious peripherals can be plugged directly into internal PCIe slots, or connected via an external Thunderbolt connection. To prove this thesis, we designed and built a new PCIe attack platform. We discovered that a simple platform was insufficient to carry out complex attacks, so created the first PCIe attack platform that runs a full, conventional OS. To allows us to conduct attacks against higher-level OS functionality built on PCIe, we made the attack platform emulate in detail the behaviour of an Intel 82574L Network Interface Controller (NIC), by using a device model extracted from the QEMU emulator. We discovered a number of vulnerabilities in the PCIe protocol itself, and with the way that the defence mechanisms it provides are used by modern OSs. The principal defence mechanism provided is the Input/Output Memory Management Unit (IOMMU). The remaps the address space used by peripherals in 4KiB chunks, and can prevent access to areas of address space that a peripheral should not be able to access. We found that, contrary to belief in the security community, the IOMMUs in modern systems were not designed to protect against attacks from malicious peripherals, but to allow virtual machines direct access to real hardware. We discovered that use of the IOMMU is patchy even in modern operating systems. Windows effectively does not use the IOMMU at all; macOS opens windows that are shared by all devices; Linux and FreeBSD map windows into host memory separately for each device, but only if poorly documented boot flags are used. These OSs make no effort to ensure that only data that should be visible to the devices is in the mapped windows. We created novel attacks that subverted control flow and read private data against systems running macOS, Linux and FreeBSD with the highest level of relevant protection enabled. These represent the first use of the relevant exploits in each case. In the final part of this thesis, we evaluate the suitability of a number of proposed general purpose and specific mitigations against DMA attacks, and make a number of recommendations about future directions in IOMMU software and hardware.EPSRC and ARM iCASE Awar

Poll-optimized adaptation of PCI-express

CPUs monitor the network interface by spin-loop polling or by the use of interrupts. Spin-loop polling delivers high performance but consumes significant amounts of power and generates heat. The use of interrupts is less power hungry but causes substantial latency. This disclosure describes techniques that introduce, for certain CPU requests, a bounded (\u3c10 μs or so) delay in the return of a completion packet from the peripheral device to the CPU. This reduces the energy spent by the CPU on read/compare/repeat loops and enables operations like direct memory access to get more bandwidth while retaining the high performance of spin-loop polling. The techniques leverage the multiple-outstanding-transactions and out-of-order completions features of the PCIe (or similar) buses to achieve zero or near-zero delay penalties while substantially mitigating the power and thermal consequences of spin-loop polling

PCI Express Bridge

Cílem diplomové práce bylo navrhnout a implementovat jednotku pro řízení protokolu sběrnice PCI Express. Jednotka má za úkol výrazným způsobem zjednodušit práci uživatelům - aplikačním inženýrům, kteří pracují na vývoji rozličných akcelerátorů pro čipy FPGA. Navržená jednotka transformuje komplexní rozhraní sběrnice PCI Express a nabízí uživateli obecnější a snadno škálovatelné rozhraní interní sběrnice pro připojení vnitřních komponent čipu. To umožňuje uživateli soustředit se pouze na vývoj cílové aplikace. Jednotka byla implementována v jazyce VHDL, dále byla provedená syntéza do hradlových polí s technologií Virtex-5 a zároveň byla otestovaná přímo na kartách ML555 a COMBOv2. Dosažené výsledky ukazují schopnost pracovat na maximální možné propustnosti, tedy na 7Gb/s.The aim of this thesis was to design and implement PCI Express Bridge. The main purpose of this unit is to help application engineers who develop various FPGA based accelerators. The implemented unit transforms complex PCI Express based system bus interface to more common and scalable interface of internal bus for on-chip components interconnection. This allows engineers to focus on the development of their target applications, not on a complicated communication protocol. The unit was implemented in the VHDL language, synthesized for Virtex-5 based FPGAs as well as completely tested on ML555 and COMBOv2 cards. The acquired results show that the component reaches the throughput of 7 Gb/s, which is the theoretical limitation of underlying protocols.

Energy-Efficient Considerations on a Variable-Bitrate PCI-Express Device

Dynamic power management has been adopted in many systems to reduce the power/energy consumption by changing the system state dynamically. This paper explores energy efficiency for systems equipped with PCI-Express devices, which are designed for low power consumption and high performance, compared to corresponding PCI devices. We propose dynamic power management mechanism and a management policy for energy-efficient considerations. A case study for a variable-bit-rate local-area-network device under the PCI-Express specification is exploited to provide supports for dynamic packet transmission. Simulation results show that the proposed mechanism and policy would reduce the system energy consumption substantiall

High throughput accelerator interface framework for a linear time-multiplexed FPGA overlay

Coarse-grained FPGA overlays improve design productivity through software-like programmability and fast compilation. However, the effectiveness of overlays as accelerators is dependent on suitable interface and programming integration into a typically processor-based computing system, an aspect which has often been neglected in evaluations of overlays. We explore the integration of a time-multiplexed FPGA overlay over a server-class PCI Express interface. We show how this integration can be optimised to maximise performance, and evaluate the area overhead. We also propose a user-friendly programming model for such an overlay accelerator system

SoPC-based DMA for PCI Express DAQ cards

This paper presents low-cost, configurable PCIExpress (PCIe) direct memory access (DMA) interface forimplementation on Intel Cyclone V FPGAs. The DMA engine wasdesigned to support DAQ tasks including continuous pretriggeringacquisition for transient analysis and multichanneltransmission. Proposed solution is based on Intel SoPC resources.Performance of the interface has been evaluated on Terasic OVSKboard (PCIe Gen2 x4). Target configuration of this interface isbased on the Avalon-MM Hard IP for Cyclone V PCIe core andJungo WinDriver x64 for Windows. A sample speed of 1200 MB/shas been reported for DMA writes to PCIe memory

High speed backbone for FPGA at ESS

The purpose of this project is to reverse engineer and re-design a PCI Express communication system which is currently being used at ESS in Lund. The current model is non-modifiable and our goal is to create a system open for customization. The aspects explored are communication between hardware and software using PCI Express, data handling and arbitration, direct memory access and how these can be implemented in hardware. We have successfully re-created the original design with a fully utilized read interface and a significantly slower write interface. The write function has been studied to find possible options to improve the current design. This system will be installed in 150 different parts of the accelerator and although it is a small part, it will be vital for the overall performance.What we have done is to reverse engineer a PCI Express (PCIe) communication system between customized hardware and a Linux computer. The original hardware design is non-modifiable and our goal is to create a system open for customization. We have successfully re-created the original design and researched possible improvements. This system will be installed in 150 different parts of the European Spallation Source (ESS). Although it is a small part, it will be vital for the overall performance of the facility