1,455 research outputs found
Survey on Combinatorial Register Allocation and Instruction Scheduling
Register allocation (mapping variables to processor registers or memory) and
instruction scheduling (reordering instructions to increase instruction-level
parallelism) are essential tasks for generating efficient assembly code in a
compiler. In the last three decades, combinatorial optimization has emerged as
an alternative to traditional, heuristic algorithms for these two tasks.
Combinatorial optimization approaches can deliver optimal solutions according
to a model, can precisely capture trade-offs between conflicting decisions, and
are more flexible at the expense of increased compilation time.
This paper provides an exhaustive literature review and a classification of
combinatorial optimization approaches to register allocation and instruction
scheduling, with a focus on the techniques that are most applied in this
context: integer programming, constraint programming, partitioned Boolean
quadratic programming, and enumeration. Researchers in compilers and
combinatorial optimization can benefit from identifying developments, trends,
and challenges in the area; compiler practitioners may discern opportunities
and grasp the potential benefit of applying combinatorial optimization
Advanced software techniques for space shuttle data management systems Final report
Airborne/spaceborn computer design and techniques for space shuttle data management system
Techniques for the realization of ultrareliable spaceborne computers Interim scientific report
Error-free ultrareliable spaceborne computer
C-MOS array design techniques: SUMC multiprocessor system study
The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units
THE APPLICATION OF REAL-TIME SOFTWARE IN THE IMPLEMENTATION OF LOW-COST SATELLITE RETURN LINKS
Digital Signal Processors (DSPs) have evolved to a level where it is feasible
for digital modems with relatively low data rates to be implemented entirely with
software algorithms. With current technology it is still necessary for analogue
processing between the RF input and a low frequency IF but, as DSP technology
advances, it will become possible to shift the interface between analogue and digital
domains ever closer towards the RF input. The software radio concept is a long-term
goal which aims to realise software-based digital modems which are completely
flexible in terms of operating frequency, bandwidth, modulation format and source
coding. The ideal software radio cannot be realised until DSP, Analogue to Digital
(A/D) and Digital to Analogue (D/A) technology has advanced sufficiently. Until
these advances have been made, it is often necessary to sacrifice optimum
performance in order to achieve real-time operation. This Thesis investigates practical
real-time algorithms for carrier frequency synchronisation, symbol timing
synchronisation, modulation, demodulation and FEC. Included in this work are novel
software-based transceivers for continuous-mode transmission, burst-mode
transmission, frequency modulation, phase modulation and orthogonal frequency
division multiplexing (OFDM).
Ideal applications for this work combine the requirement for flexible baseband
signal processing and a relatively low data rate. Suitable applications for this work
were identified in low-cost satellite return links, and specifically in asymmetric
satellite Internet delivery systems. These systems employ a high-speed (>>2Mbps)
DVB channel from service provider to customer and a low-cost, low-speed (32-128
kbps) return channel. This Thesis also discusses asymmetric satellite Internet delivery
systems, practical considerations for their implementation and the techniques that are
required to map TCP/IP traffic to low-cost satellite return links
Constraint analysis for DSP code generation
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