194 research outputs found
Differential temperature sensors: Review of applications in the test and characterization of circuits, usage and design methodology
Differential temperature sensors can be placed in integrated circuits to extract a signature ofthe power dissipated by the adjacent circuit blocks built in the same silicon die. This review paper firstdiscusses the singularity that differential temperature sensors provide with respect to other sensortopologies, with circuit monitoring being their main application. The paper focuses on the monitoringof radio-frequency analog circuits. The strategies to extract the power signature of the monitoredcircuit are reviewed, and a list of application examples in the domain of test and characterizationis provided. As a practical example, we elaborate the design methodology to conceive, step bystep, a differential temperature sensor to monitor the aging degradation in a class-A linear poweramplifier working in the 2.4 GHz Industrial Scientific MedicalâISMâband. It is discussed how,for this particular application, a sensor with a temperature resolution of 0.02 K and a high dynamicrange is required. A circuit solution for this objective is proposed, as well as recommendations for thedimensions and location of the devices that form the temperature sensor. The paper concludes with adescription of a simple procedure to monitor time variability.Postprint (published version
Solutions pour l'auto-adaptation des systĂšmes sans fil
The current demand on ubiquitous connectivity imposes stringent requirements on the fabrication of Radio-Frequency (RF) circuits. Designs are consequently transferred to the most advanced CMOS technologies that were initially introduced to improve digital performance. In addition, as technology scales down, RF circuits are more and more susceptible to a lot of variations during their lifetime, as manufacturing process variability, temperature, environmental conditions, aging⊠As a result, the usual worst-case circuit design is leading to sub-optimal conditions, in terms of power and/or performance most of the time for the circuit. In order to counteract these variations, increasing the performances and also reduce power consumption, adaptation strategies must be put in place.More importantly, the fabrication process introduces more and more performance variability, which can have a dramatic impact on the fabrication yield. That is why RF designs are not easily fabricated in the most advanced CMOS technologies, as 32nm or 22nm nodes for instance. In this context, the performances of RF circuits need to be calibrated after fabrication so as to take these variations into account and recover yield loss.This thesis work is presenting on a post-fabrication calibration technique for RF circuits. This technique is performed during production testing with minimum extra cost, which is critical since the cost of test can be comparable to the cost of fabrication concerning RF circuits and cannot be further raised. Calibration is enabled by equipping the circuit with tuning knobs and sensors. Optimal tuning knob identification is achieved in one-shot based on a single test step that involves measuring the sensor outputs once. For this purpose, we rely on variation-aware sensors which provide measurements that remain invariant under tuning knob changes. As an auxiliary benefit, the variation-aware sensors are non-intrusive and totally transparent to the circuit.Our proposed methodology has first been demonstrated with simulation data with an RF power amplifier as a case study. Afterwards, a silicon demonstrator has then been fabricated in a 65nm technology in order to fully demonstrate the methodology. The fabricated dataset of circuits is extracted from typical and corner wafers. This feature is very important since corner circuits are the worst design cases and therefore the most difficult to calibrate. In our case, corner circuits represent more than the two third of the overall dataset and the calibration can still be proven. In details, fabrication yield based on 3 sigma performance specifications is increased from 21% to 93%. This is a major performance of the technique, knowing that worst case circuits are very rare in industrial fabrication.La demande courante de connectivitĂ© instantanĂ©e impose un cahier des charges trĂšs strict sur la fabrication des circuits Radio-FrĂ©quences (RF). Les circuits doivent donc ĂȘtre transfĂ©rĂ©es vers les technologies les plus avancĂ©es, initialement introduites pour augmenter les performances des circuits purement numĂ©riques. De plus, les circuits RF sont soumis Ă de plus en plus de variations et cette sensibilitĂ© sâaccroĂźt avec lâavancĂ©es des technologies. Ces variations sont par exemple les variations du procĂ©dĂ© de fabrication, la tempĂ©rature, lâenvironnement, le vieillissement⊠Par consĂ©quent, la mĂ©thode classique de conception de circuits âpire-casâ conduit Ă une utilisation non-optimale du circuit dans la vaste majoritĂ© des conditions, en termes de performances et/ou de consommation. Ces variations doivent donc ĂȘtre compensĂ©es, en utilisant des techniques dâadaptation.De maniĂšre plus importante encore, le procĂ©dĂ© de fabrication des circuits introduit de plus en plus de variabilitĂ© dans les performances des circuits, ce qui a un impact important sur le rendement de fabrication des circuits. Pour cette raison, les circuits RF sont difficilement fabriquĂ©s dans les technologies CMOS les plus avancĂ©es comme les nĆuds 32nm ou 22nm. Dans ce contexte, les performances des circuits RF doivent ĂȘtres calibrĂ©es aprĂšs fabrication pour prendre en compte ces variations et retrouver un haut rendement de fabrication.Ce travail de these prĂ©sente une mĂ©thode de calibration post-fabrication pour les circuits RF. Cette mĂ©thodologie est appliquĂ©e pendant le test de production en ajoutant un minimum de coĂ»t, ce qui est un point essentiel car le coĂ»t du test est aujourdâhui dĂ©jĂ comparable au coĂ»t de fabrication dâun circuit RF et ne peut ĂȘtre augmentĂ© dâavantage. Par ailleurs, la puissance consommĂ©e est aussi prise en compte pour que lâimpact de la calibration sur la consommation soit minimisĂ©. La calibration est rendue possible en Ă©quipant le circuit avec des nĆuds de rĂ©glages et des capteurs. Lâidentification de la valeur de rĂ©glage optimale du circuit est obtenue en un seul coup, en testant les performances RF une seule et unique fois. Cela est possible grĂące Ă lâutilisation de capteurs de variations du procĂ©dĂ© de fabrication qui sont invariants par rapport aux changements des nĆuds de rĂ©glage. Un autre benefice de lâutilisation de ces capteurs de variation sont non-intrusifs et donc totalement transparents pour le circuit sous test. La technique de calibration a Ă©tĂ© dĂ©montrĂ©e sur un amplificateur de puissance RF utilisĂ© comme cas dâĂ©tude. Une premiĂšre preuve de concept est dĂ©veloppĂ©e en utilisant des rĂ©sultats de simulation.Un dĂ©monstrateur en silicium a ensuite Ă©tĂ© fabriquĂ© en technologie 65nm pour entiĂšrement dĂ©montrer le concept de calibration. Lâensemble des puces fabriquĂ©es a Ă©tĂ© extrait de trois types de wafer diffĂ©rents, avec des transistors aux performances lentes, typiques et rapides. Cette caractĂ©ristique est trĂšs importante car elle nous permet de considĂ©rer des cas de procĂ©dĂ© de fabrication extrĂȘmes qui sont les plus difficiles Ă calibrer. Dans notre cas, ces circuits reprĂ©sentent plus des deux tiers des puces Ă disposition et nous pouvons quand mĂȘme prouver notre concept de calibration. Dans le dĂ©tails, le rendement de fabrication passe de 21% avant calibration Ă plus de 93% aprĂšs avoir appliquĂ© notre mĂ©thodologie. Cela constitue une performance majeure de notre mĂ©thodologie car les circuits extrĂȘmes sont trĂšs rares dans une fabrication industrielle
BPF-based thermal sensor circuit for on-chip testing of RF circuits
A new sensor topology meant to extract figures of merit of radio-frequency analog integrated circuits (RF-ICs) was experimentally validated. Implemented in a standard 0.35 ”m complementary metal-oxide-semiconductor (CMOS) technology, it comprised two blocks: a single metaloxide-semiconductor (MOS) transistor acting as temperature transducer, which was placed near the circuit to monitor, and an active band-pass filter amplifier. For validation purposes, the temperature sensor was integrated with a tuned radio-frequency power amplifier (420 MHz) and MOS transistors acting as controllable dissipating devices. First, using the MOS dissipating devices, the performance and limitations of the different blocks that constitute the temperature sensor were characterized. Second, by using the heterodyne technique (applying two nearby tones) to the power amplifier (PA) and connecting the sensor output voltage to a low-cost AC voltmeter, the PAâs output power and its central frequency were monitored. As a result, this topology resulted in a low-cost approach, with high linearity and sensitivity, for RF-IC testing and variability monitoring.This research was funded by Spanish AEIâAgencia Estatal de InvestigaciĂłnâgrant number PID2019-103869RB-C33. (X.P.) has also received founds from the Spanish Ministry of Science,
Innovation and Universities through Agencia Estatal de InvestigaciĂłn (AEI) (projects: HIPERCELLS,
RTI2018-098392B-I00, and âFiabilidad Inteligenteâ, PCI2020-112028).Peer ReviewedPostprint (published version
DESIGN OF SMART SENSORS FOR DETECTION OF PHYSICAL QUANTITIES
Microsystems and integrated smart sensors represent a flourishing business thanks to the manifold benefits of these devices with respect to their respective macroscopic counterparts. Miniaturization to micrometric scale is a turning point to obtain high sensitive and reliable devices with enhanced spatial and temporal
resolution. Power consumption compatible with battery operated systems, and reduced cost per device are also pivotal for their success. All these characteristics make investigation on this filed very active nowadays.
This thesis work is focused on two main themes: (i) design and development of a single chip smart flow-meter; (ii) design and development of readout interfaces for capacitive micro-electro-mechanical-systems (MEMS) based on capacitance to pulse width modulation conversion.
High sensitivity integrated smart sensors for detecting very small flow rates of both gases and liquids aiming to fulfil emerging demands for this kind of devices in the industrial to environmental and medical applications. On the other hand, the prototyping of such sensor is a multidisciplinary activity involving the study of
thermal and fluid dynamic phenomenon that have to be considered to obtain a correct design. Design, assisted by finite elements CAD tools, and fabrication of the sensing structures using features of a standard CMOS process is discussed in the first chapter. The packaging of fluidic sensors issue is also illustrated as it has a
great importance on the overall sensor performances. The package is charged to allow optimal interaction between fluids and the sensors and protecting the latter from the external environment. As miniaturized structures allows a great spatial resolution, it is extremely challenging to fabricate low cost packages for multiple flow rate measurements on the same chip. As a final point, a compact anemometer prototype, usable for wireless sensor network nodes, is described.
The design of the full custom circuitry for signal extraction and conditioning is coped in the second chapter, where insights into the design methods are given for analog basic building blocks such as amplifiers, transconductors, filters, multipliers,
current drivers. A big effort has been put to find reusable design guidelines and
trade-offs applicable to different design cases. This kind of rational design enabled the implementation of complex and flexible functionalities making the interface circuits able to interact both with on chip sensors and external sensors.
In the third chapter, the chip floor-plan designed in the STMicroelectronics BCD6s
process of the entire smart flow sensor formed by the sensing structures and the readout electronics is presented. Some preliminary tests are also covered here.
Finally design and implementation of very low power interfaces for typical MEMS
capacitive sensors (accelerometers, gyroscopes, pressure sensors, angular displacement and chemical species sensors) is discussed. Very original circuital topologies, based on chopper modulation technique, will be illustrated. A prototype, designed within a joint research activity is presented. Measured performances
spurred the investigation of new techniques to enhance precision and accuracy capabilities of the interface.
A brief introduction to the design of active pixel sensors interface for hybrid CMOS
imagers is sketched in the appendix as a preliminary study done during an internship in the CNM-IMB institute of Barcelona
Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP
International audienceIn this paper, we propose a defect-oriented Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/M-S) Integrated Circuits (ICs), called symmetry-based BIST (Sym-BIST). SymBIST exploits inherent symmetries into the design to generate invariances that should hold true only in defect-free operation. Violation of any of these invariances points to defect detection. We demonstrate SymBIST on a 65nm 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP by ST Microelectronics
Low-power Wearable Healthcare Sensors
Advances in technology have produced a range of on-body sensors and smartwatches that can be used to monitor a wearerâs health with the objective to keep the user healthy. However, the real potential of such devices not only lies in monitoring but also in interactive communication with expert-system-based cloud services to offer personalized and real-time healthcare advice that will enable the user to manage their health and, over time, to reduce expensive hospital admissions. To meet this goal, the research challenges for the next generation of wearable healthcare devices include the need to offer a wide range of sensing, computing, communication, and humanâcomputer interaction methods, all within a tiny device with limited resources and electrical power. This Special Issue presents a collection of six papers on a wide range of research developments that highlight the specific challenges in creating the next generation of low-power wearable healthcare sensors
Design of a CMOS power amplifier and built-in sensors for variability monitoring and compensation
This research thesis aims to develop a system composed by a a CMOS power amplifier and built-in sensors for variability monitoring and compensation. The integration of monitoring systems with high frequency analog circuits is commonly used for performance optimization and control. In addition, built-in sensors are used in quality testing, improving the yield by detecting circuit faults during the fabrication of these. Typically, most of the built-in sensors are electrically connected to a node of the circuit under test, affecting its performance. In tuned power amplifers, for instance, a small load variation can cause a degradation of its output power and effciency. Hence, the integration between the circuit under test and the monitoring block should be carefully designed. These loading effects can be avoided using non-invasive solutions such as temperature sensors. An integrated circuit composed by a CMOS power amplifer, two amplitude detectors and a temperature sensor is implemented in this work. The degradation of the power amplifier performance due to variability effects is accelerated by increasing its supply voltage. A feedback loop is added to control and adjust the system operation, stress the amplifier and accelerate its degradation, monitor the amplifier performance using the sensors and compensate the observed degradation. The design of each one of the main parts of the system is presented through this work, explaining their theoretical basis and validating their operation with simulations results. Finally, all the parts are integrated together, and a feedback loop with a control algorithm is proposed to monitor and compensate the DUT variability effects
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Low-Power Integrated Circuits For Biomedical Applications
With thousands new cases of spinal cord injury reported everyday, many people suffer from paralysis and loss of sensation in both legs. Beside the healthcare costs, such a state severely deteriorates the patients' quality of life and may even lead to additional medical conditions. Therefore, there is a growing need for cyber-physical systems to restore the walking ability through bypassing the damaged spinal cord. This goal can be achieved by monitoring and processing patient's brain signals to enable brain-directed control of prosthetic legs. Among several existing methods to record brain signals, electrocorticography (ECoG) has gained popularity due to being robust to motion artifacts, having high spatial resolution and signal to noise ratio, being moderately invasive and the possibility of chronic implantation of recording grids with no or minor scar tissue formation. The latest property is of particular importance for the whole system to be a viable fully implantable solution. Furthermore, the implanted system has to operate independently with no or minimal need of external hardware (e.g. a bulky personal computer) to be individually and socially accepted. To implement a fully implantable system, low-power and miniaturized electronics are needed to reduced heat generation, increase battery life-time and be minimally intrusive. These requirements indicate that many of the system's components should be custom-designed to integrated as much functionality as possible in a given real estate. This thesis presents silicon tested prototypes of several building blocks for the envisioned system, namely, ultra low-power brain signal acquisition front-ends, a low-power and inductorless MedRadio transceiver, and a fast start-up crystal oscillator. Brain signal acquisition front-ends provide low noise amplification of weak ECoG biosignals. MedRadio transceiver enables communication between the implant and end effectors or base station (e.g. prosthetic legs or desktop computer). Crystal oscillator generates the reference signal for other system's components such as analog to digital converter. Novel techniques to improve important performance parameters (power consumption, low noise operation and interference resilience) have been introduced. Electrical, in-vitro and in-vivo experimental measurements have verified the functionality and performance of each design
On-Chip Integrated Functional Near Infra-Red Spectroscopy (fNIRS) Photoreceiver for Portable Brain Imaging
RĂSUMĂ
L'imagerie cérébrale fonctionnelle utilisant la Spectroscopie Fonctionnelle Proche-Infrarouge (SFPI)
propose un outil portatif et non invasif de surveillance de l'oxygénation du sang. SFPI est une technique de
haute rĂ©solution temporelle non invasive, sĂ»r, peu intrusive en temps rĂ©el et pour l'imagerie cĂ©rĂ©brale Ă
long terme. Il permet de détecter des signaux hémodynamiques à la fois rapides et neuronaux ou lents. Outre les avantages importants des systÚmes SFPI, ils souffrent encore de quelques inconvénients,
notamment dâune faible rĂ©solution spatiale, dâun bruit de niveau modĂ©rĂ©ment Ă©levĂ© et dâune grande
sensibilité au mouvement. Afin de surmonter les limites des systÚmes actuellement disponibles de SFPI non-portables, dans cette thÚse, nous en avons introduit une nouvelle de faible puissance, miniaturisée sur une puce photodétecteur frontal destinée à des systÚmes de SFPI portables. Elle contient du silicium
photodiode à avalanche (SiAPD), un amplificateur de transimpédance (TIA), et « Quench-Reset », circuits
mis en oeuvre en utilisant les technologies CMOS standards pour fonctionner dans les deux modes :
linĂ©aire et Geiger. Ainsi, elle peut ĂȘtre appliquĂ©e pour les deux fNIRS : en onde continue (CW- SFPI) et
pour des applications de comptage de photon unique. Plusieurs SiAPDs ont été mises en oeuvre dans de nouvelles structures et formes (rectangulaires, octogonales, double APDs, imbriquées, netted, quadratiques et hexadecagonal) en utilisant différentes techniques de prévention de la dégradation de bord
prématurée. Les principales caractéristiques des SiAPDs sont validées et l'impact de chaque paramÚtre ainsi que les simulateurs de l'appareil (TCAD, COMSOL, etc) ont été étudiés sur la base de la simulation et de mesure des résultats. Proposées SiAPDs techniques d'exposition avec un gain de grande avalanche,
tension faible ventilation et une grande efficacitĂ© de dĂ©tection des photons dans plus de faibles taux de comptage sombres. Trois nouveaux produits Ă haut gain, bande passante (GBW) et Ă faible bruit TIA sont introduits basĂ©s sur le concept de gain distribuĂ©, dâamplificateur logarithmique et sur le rejet automatique
du bruit pour ĂȘtre appliquĂ© en mode de fonctionnement linĂ©aire. Le TIA proposĂ© offre une faible consommation, un gain de haute transimpĂ©dance, une bande passante ajustable et un trĂšs faible bruit
d'entrée et de sortie. Le nouveau circuit mixte trempe-reset (MQC) et un MQC contrÎlable (CMQC)
frontaux offrent une faible puissance, une haute vitesse de comptage de photons avec un commandable de
temps de hold-off et temps de réinitialiser. La premiÚre intégration sur puce de SiAPDs avec TIA et Photon circuit de comptage a été démontrée et montre une amélioration de l'efficacité de la
photodétection, spécialement en ce qui concerne la sensibilité, la consommation d'énergie et le rapport signal sur bruit.----------ABSTRACT
Optical brain imaging using functional near infra-red spectroscopy (fNIRS) offers a direct and
noninvasive tool for monitoring of blood oxygenation. fNIRS is a noninvasive, safe, minimally
intrusive, and high temporal-resolution technique for real-time and long-term brain imaging. It allows detecting both fast-neuronal and slow-hemodynamic signals. Besides the significant
advantages of fNIRS systems, they still suffer from few drawbacks including low spatial-
resolution, moderately high-level noise and high-sensitivity to movement. In order to overcome
the limitations of currently available non-portable fNIRS systems, we have introduced a new
low-power, miniaturized on-chip photodetector front-end intended for portable fNIRS systems. It
includes silicon avalanche photodiode (SiAPD), Transimpedance amplifier (TIA), and Quench-
Reset circuitry implemented using standard CMOS technologies to operate in both linear and
Geiger modes. So it can be applied for both continuous-wave fNIRS (CW-fNIRS) and also
single-photon counting applications. Several SiAPDs have been implemented in novel structures
and shapes (Rectangular, Octagonal, Dual, Nested, Netted, Quadratic and Hexadecagonal) using
different premature edge breakdown prevention techniques. The main characteristics of the
SiAPDs are validated and the impact of each parameter and the device simulators (TCAD,
COMSOL, etc.) have been studied based on the simulation and measurement results. Proposed
techniques exhibit SiAPDs with high avalanche-gain (up to 119), low breakdown-voltage (around
12V) and high photon-detection efficiency (up to 72% in NIR region) in additional to a low dark-
count rate (down to 30Hz at 1V excess bias voltage). Three new high gain-bandwidth product
(GBW) and low-noise TIAs are introduced and implemented based on distributed-gain concept,
logarithmic-amplification and automatic noise-rejection and have been applied in linear-mode of operation. The implemented TIAs offer a power-consumption around 0.4 mW, transimpedance gain of 169 dBΩ, and input-output current/voltage noises in fA/pV range accompanied with ability to tune the gain, bandwidth and power-consumption in a wide range. The implemented
mixed quench-reset circuit (MQC) and controllable MQC (CMQC) front-ends offer a quenchtime of 10ns, a maximum power-consumption of 0.4 mW, with a controllable hold-off and resettimes. The on-chip integration of SiAPDs with TIA and photon-counting circuitries has been demonstrated showing improvement of the photodetection-efficiency, specially regarding to the
sensitivity, power-consumption and signal-to-noise ratio (SNR) characteristics
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