Area Efficient Device Optimization for ESD Protection in High Speed Interface ICs

Electrostatic discharge (ESD) protection is considered as a vital step in integrated circuit (IC) manufacturing process. IC chips are unable to overcome the effects of transient events without adequate discharge protection. Recent trend in the industry has seen the incorporation of system level ESD protection within the IC chip. Incorporating system level on-chip ESD protection often increases cost, degrades circuit performance and consumes layout area which could otherwise be used for improving the circuit performance. These design challenges could be easily overcome if the parasitic components in a circuit were used for ESD protection. Despite the various design challenges, on-chip ESD protection is still desirable as it saves the area on the circuit board by eliminating the traditional ESD protection devices resulting in more compact circuits. Furthermore, using parasitic components while designing on-chip system level ESD protection can save layout area. In order to effectively implement this solution, a study on ESD events, protection circuits and high-speed ICs was carried out. Different types of ESD events and the different models pertaining to ESD events were studied and are discussed in detail. An overview of high-speed integrated circuits was also carried out with emphasis on the protection topologies that are commonly used. The ESD characteristics of parasitic PNP devices in rail-based ESD protection structure was then studied to summarize its viability as a protection circuit. The turn-on or breakdown voltage of the parasitic PNP is studied by technology computer aided design (TCAD) simulations performed in Silvaco software. The breakdown voltage, holding voltage, on resistance and failure current were studied and modeled to maximize ESD protection

Optimization and modeling of ESD protection devices

“Transient voltage suppressors (TVS) are used to protect ICs (integrated circuits) against overvoltage, ESD (Electrostatic Discharge), inductive load switching, and even lightning strikes. In this research, a transient behavior model framework for ESD protection devices is used for modelling four different types of TVS (non-snapback, snapback, spark gap like device and varistor). The System-Efficient ESD Design (SEED) methodology is utilized to strengthen the trust in the model framework by efficient simulation of ESD interaction of the off-chip ESD protection devices with the IC ESD protection device and associated measurement data. Improvements in the TVS transient response, accounting for conductivity modulation, voltage overshot at the snapback voltage, etc., are required to accurately model the ESD protection device. With this in mind, the unimproved model is presented for various ESD protection device where their transient behavior of single component can be fully described by a quasistatic very fast transmission line pulse (VF)-TLP. The improved model is validated within a sub-system consisting of an off-chip ESD protection device, an IC on-chip protection and a PCB trace in between. Multiple solutions to avoid convergence issues are also proposed for effective simulation”--Abstract, page iv

Characterisation of on-chip electrostatic discharge waveforms with sub-nanosecond resolution: design of a differential high voltage probe with high bandwidth

Bliksem werd tot aan de ontdekking van de bliksemafleider (18e eeuw) gezien als een van de gevaarlijkste bedreigingen voor het stadsleven. Door het gebruik van micro-elektronica werden ingenieurs gewaar dat ditzelfde fysische verschijnsel, elektrostatische ontlading of ESD genoemd, zich ook op microscopische schaal voordoet. In de jaren zeventig was meer dan 30% van al het chipfalen te wijten aan ESD. Om dit tegen te gaan werd met het onderzoek naar ESD-protecties en -meetsystemen aangevangen. Om meer informatie over het gedrag van een ESD-protectie te verkrijgen wordt een ESD-puls op dit systeem losgelaten. Het antwoord van de protectie op deze puls wordt dan bepaald m.b.v. spannings- en stroomgolfvormmetingen. In dit werk wordt een nieuwe nauwkeurige ESD-golfvormmeettechniek voorgesteld die directe metingen op protecties kan uitvoeren. De karakterisering van ESD-golfvormen op chip wordt enorm bemoeilijkt door de grote hoeveelheid elektromagnetische interferentie die de ESD-puls veroorzaakt. Dit wordt omzeild door het gewenste signaal naar een veilige omgeving te transporteren, waar een standaard meettoestel de meting kan uitvoeren. Dit transport wordt gerealiseerd m.b.v. optische communicatie, wat immuun is voor elektromagnetische interferentie. Zo kan nauwkeurige in-situ-informatie worden verkregen waarmee de ESD-protecties in de toekomst verbeterd kunnen worden.Up to the 18th century, lightning was considered one of nature’s most dangerous threats in city life. This all ended with the lightning rod, protecting thousands of homes during lightning storms. The large-scale use of microelectronics has made engineers aware of the same physical phenomenon occuring on a microscopic scale. This phenomenon is called electrostatic discharge or ESD. In the seventies, more than 30% of all chip failure was attributed to static electricity. To counter this effect, the research for on-chip ESD protections was born. Today ESD is a buzzing line of research, as with new and faster chip technologies comes a higher ESD vulnerability. This makes ESD protection and measurement increasingly important. Although ESD is now a major subject in chip design, it copes with a lack of accurate device models. To gain more information on the exact operation of an ESD protection, an ESD pulse is unleashed upon this device. The response of the protection on this pulse is then assessed by performing voltage or current waveform measurements. This work presents a waveform measurement technique able to accurately perform direct measurements on the ESD protection. Due to the high amount of electromagnetic interference caused by the ESD pulse, direct waveform characterisation near the protection is hard. This is solved by transporting the target signal into a clean area, where the measurement is performed by standard lab equipment. The key is that this transportation is realized by means of optical communication, which is immune to electromagnetic interference. This way, accurate in situ information can be used to protect tomorrow’s chips

Design of high frequency circuits for a gigabit per second data transmission system with isolation transformers and improved electrostatic protection

The focus of this dissertation is the design of a 10 Gbit/s wireline data communication system. The data is sent from the driver chip to the receiver chip on a printed circuit board (PCB). In the GHz frequency range, the parasitic effect of various circuits along the signal path affect the quality of the signal sent. Electrostatic Discharge (ESD) protection, PCB traces and packaging increase the signal loss and distortion;The parasitic effect of ESD protection circuits limits the maximum bandwidth for data transmission. The current high speed driver architectures have the driver circuit directly connected to the chip pads and PCB traces. This causes the chip to be prone to ESD discharge effects. Placing large ESD devices that shunt the output driver to ground, results in their parasitic capacitances acting as low pass filters that severely limit the data transmission rate. The packaging and PCB material are investigated in this project too. An electrical model of the bonding wire is developed through MATLAB RTM and HSPICERTM;In order to increase the data rate, changes in the architecture are performed. The contribution of this project is the introduction of on chip monolithic 4 port RF transformers at the driver and receiver front-end circuits. The transformers act as ESD isolation devices because they filter the low frequency components of the ESD signals before they damage the driver. The driver is physically isolated from the chip exterior. The signal in the driver is conveyed to the traces outside the chip by transformer induction behavior. Spark gap devices are added as ESD discharge paths too. Through investigating several transformer architectures, planar interleaved transformers are fabricated and characterized to have a bandwidth beyond 5GHz needed for suitable data transmission. A design and characterization method of RF transformers by geometric scaling is presented;The transformers are used in the driver and receiver circuit. Through simulation, the improved design proves to increase the bandwidth of the data link significantly

Design, Characterization And Compact Modeling Of Novel Silicon Controlled Rectifier (scr)-based Devices For Electrostatic Discha

Electrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have been standardized as human body model (HBM), machine model (MM), charged device model (CDM) and international electrotechnical commission model (IEC) for control, monitor and test. In additional to the environmental control of ESD events during manufacturing, shipping and assembly, incorporating on-chip ESD protection circuits inside ICs is another effective solution to reduce the ESD-induced damage. This dissertation presents design, characterization, integration and compact modeling of novel silicon controlled rectifier (SCR)-based devices for on-chip ESD protection. The SCR-based device with a snapback characteristic has long been used to form a VSS-based protection scheme for on-chip ESD protection over a broad rang of technologies because of its low on-resistance, high failure current and the best area efficiency. The ESD design window of the snapback device is defined by the maximum power supply voltage as the low edge and the minimum internal circuitry breakdown voltage as the high edge. The downscaling of semiconductor technology keeps on squeezing the design window of on-chip ESD protection. For the submicron process and below, the turn-on voltage and sustain voltage of ESD protection cell should be lower than 10 V and higher than 5 V, respectively, to avoid core circuit damages and latch-up issue. This presents a big challenge to device/circuit engineers. Meanwhile, the high voltage technologies push the design window to another tough range whose sustain voltage, 45 V for instance, is hard for most snapback ESD devices to reach. Based on the in-depth elaborating on the principle of SCR-based devices, this dissertation first presents a novel unassisted, low trigger- and high holding-voltage SCR (uSCR) which can fit into the aforesaid ESD design window without involving any extra assistant circuitry to realize an area-efficient on-chip ESD protection for low voltage applications. The on-chip integration case is studied to verify the protection effectiveness of the design. Subsequently, this dissertation illustrate the development of a new high holding current SCR (HHC-SCR) device for high voltage ESD protection with increasing the sustain current, not the sustain voltage, of the SCR device to the latchup-immune level to avoid sacrificing the ESD protection robustness of the device. The ESD protection cells have been designed either by using technology computer aided design (TCAD) tools or through trial-and-error iterations, which is cost- or time-consuming or both. Also, the interaction of ESD protection cells and core circuits need to be identified and minimized at pre-silicon stage. It is highly desired to design and evaluate the ESD protection cell using simulation program with integrated circuit emphasis (SPICE)-like circuit simulation by employing compact models in circuit simulators. And the compact model also need to predict the response of ESD protection cells to very fast transient ESD events such as CDM event since it is a major ESD failure mode. The compact model for SCR-based device is not widely available. This dissertation develops a macromodeling approach to build a comprehensive SCR compact model for CDM ESD simulation of complete I/O circuit. This modeling approach offers simplicity, wide availability and compatibility with most commercial simulators by taking advantage of using the advanced BJT model, Vertical Bipolar Inter-Company (VBIC) model. SPICE Gummel-Poon (SGP) model has served the ICs industry well for over 20 years while it is not sufficiently accurate when using SGP model to build a compact model for ESD protection SCR. This dissertation seeks to compare the difference of SCR compact model built by using VBIC and conventional SGP in order to point out the important features of VBIC model for building an accurate and easy-CAD implement SCR model and explain why from device physics and model theory perspectives

Measurement and Analysis of Electromagnetic Field, Noise and IC Logic Error due to system-level ESD

Department of Electrical EngineeringAs the high performance very-large-scale integration (VLSI) systems operate with high speed and low voltage, the system-level electrostatic discharge (ESD) event is becoming one of the important noise sources causing logic errors and system malfunctions such as system reboot or fault. To understand the ESD noise phenomena and improve the system-level ESD noise immunity for devices, the accurate ESD noise measurement and analysis of IC logic errors are necessary. Section I is written for the tendency of ESD research and previous research. This paper presents the noise type correlation by measuring the signal-ground noise and power-ground noise simultaneously on the fundamental F/F operation circuit and shows the type of error from chip, in section II. Furthermore, the decoupling capacitors (de-cap) effect that can reduce the error occurrence by checking the error rate are analyzed. A generator is designed on the main board which is based on real operating laptop, and the chip on dual in-line memory module (DIMM) is also designed to perform the basic F/F operation. The clock and data input from generator are connected to the chip on the DIMM through the small outline dual in-line memory module (SODIMM) socket. ESD occurs at the corner of the ground plane of main board. The specification of the ESD generator satisfies IEC 61000-4-2 [1]. The ESD current flows along the ground strap, and affects the DIMM. IN-ground, CLK-ground, OUT-ground and power-ground on the DIMM are simultaneously measured to determine the effect of ESD on the main board. To analyze the error ratio according to the ESD voltage level, the voltage setup of the ESD gun is 3kV, 5kV and 8kV. To investigate the effects of chip shielding and DIMM de-caps on the error probability of DIMM, the experiment is conducted under the several conditions. After confirming the normal operation for each condition, the error type on the DIMM due to the ESD occurred in the circuit is analyzed and the statistics are shown. The results are verified by H-spice simulation, Vector Network Analyzer (VNA) and HFSS simulation. In order to obtain the improvement method of the DIMM immunity, experiments are conducted to find out the effective position and number of DIMM de-cap. Accurate measurements of electromagnetic fields are also essential to analyze the radiated noise due to unwanted electrostatic discharge (ESD) events at electronic devices. Usually, to know the radiated noise by ESD events, the voltages induced at field probes are measured, and the fields are obtained from the voltage by de-convolving the probe factor. In section ???, the two probe-factor deconvolution methods are investigated and compared in the measurements of the fields induced by system-level ESD events.ope

Optimal design of a 2.4 GHz CMOS low noise amplifier

In most RF receivers, the Low Noise Amplifier (LNA) is normally the first component, whose performance is very critical. For the LNA architecture that uses source degeneration inductors and cascode topology, the performance depends largely on the performance of the inductors. All the parasitics associated with the inductors should be thoroughly analyzed and taken into consideration while designing the LNA. The work presented in this thesis can be broadly classified as follows: optimization of the LNA design with respect to all the parasitics associated with the on-chip spiral inductors, modeling high performance inductors, which are embedded in the silicon substrate and analysis of parasitic effects from the Electro Static Discharge (ESD) protection circuitry on the performance of the LNA. A methodology has been developed such that the LNA design can be optimized in the presence of an ESD protection circuitry in order to achieve the required input impedance match. This optimization procedure is presented for all possible placements of the ESD protection circuitry at the input of the LNA, that is, with respect to the gate inductor being realized on-chip or off-chip or a combination of on-chip and off-chip inductors. The thesis presents the procedure to vary the source inductance and gate inductance values in the presence of parasitic ESD capacitance in order to optimize LNA design such that the required input impedance match is maintained

Analysis and Design of Electrostatic Discharge Protection Devices and Circuits

An electrostatic discharge (ESD) is a spontaneous electrical current that flows between two objects at different electrical potentials. ESD currents can reach several amps and are typically in the order of tens of nanoseconds. Concerning microelectronics, on-chip protection against ESD events has become a main concern on the reliability of IC as dimensions continue to shrink. ESD currents could lead to on-chip voltages that are high enough to cause MOS gate oxide breakdown. ICs can thus be damaged by human handling, contact with machinery, packaging, board assembling, etc. The main goal of this study was to analyze the effectiveness of two-stage ESD protection circuits by means of mixed mode TCAD simulations. Two-dimensional device simulations were carried out using T-Suprem4 and Taurus-Medici software from Synopsis. Also, a TCAD input deck calibration for an NXP Semiconductors¿ proprietary 0.14m¿ CMOS technology was realized. In addition, two aspects on the transparency of ESD protections were studied. An excessive leakage problem found in a real product was analyzed in TCAD. Furthermore, a new approach for distributed ESD protection design for broadband applications is also discussed, resulting in improved RF performance.Pérez Monteagudo, JM. (2010). Analysis and Design of Electrostatic Discharge Protection Devices and Circuits. http://hdl.handle.net/10251/21061.Archivo delegad

SEED modeling of an ESD gun discharge to a USB cable

“An IC protected by a transient voltage suppression (TVS) diode may fail if the TVS device does not turn on or does not turn on quickly enough, causing the IC to take the full brunt of the electrostatic discharge (ESD) event. Transient simulation models have been developed for ESD protection devices for the purpose of system-efficient ESD design (SEED). The TVS modeling methodology has been improved to better represent the physics that occurs during the TVS response and more accurately predict the interactions between off-chip and on-chip protection devices. Moreover, a complicated test scenario -- an ESD gun discharge through a USB cable -- was investigated and simulated, to demonstrate the impact of position, grounding condition, and quality of the USB cable. Test and design guidelines are proposed for incorporating a USB cable in a contact-discharge ESD test. At the beginning, a hybrid simulation approach was proposed, which uses a full-wave model of the ESD gun, cable, and enclosure combined with the ESD protection devices and test board’s circuit-level models. The voltage and current of ESD protection devices are captured within 24-35% compared to the measurements, under various cable configurations. To further improve the simulation accuracy, physics-based modeling methodologies were proposed to improve the previously developed TVS model, especially on the falling edge after the overshoot. The ESD protection device’s response was studied in simulation and measurement for various cable configurations. And the overall discrepancy is within 30%. The modeling process can help engineers to evaluate the design effectiveness under various complicated test scenarios”--Abstract, page iv

Failures caused by supply fluctuations during system-level ESD

It is necessary to design robust electronic systems against system-level electrostatic discharge (ESD). In additional to withstanding ESD without hard failures (permanent damage), it is important that the system is robust against soft failures (recoverable loss of function or data), which can be caused by ESD-induced noise on signal inputs and power nets. Besides radiation, the current injection into the circuit alone can cause these disturbances, especially the sharp current spike of a high amplitude in system-level ESD. The waveform of this current is similar in various ESD test setups. Circuit models with distributed elements enable accurate modeling of the system-level ESD current in contact discharge. Experiments have shown that ESD-induced noise on signal traces starts to disturb the IO input at very low ESD levels, and the effectiveness of the transient voltage suppressor (TVS) on board is limited. The noise on supply is global to integrated circuit (IC), as it travels across all the power domains. The waveform of the noise depends on the polarity of the ESD current and the type of ESD protection. The experiments have shown that the supply fluctuation can be quite severe, as a strong reverse of the on-chip supply is indicated by monitor circuits starting from the ESD levels below the common required passing level. This poses a requirement of a minimum amount of on-chip decoupling capacitances (decaps) to limit the amplitude of supply fluctuations. This requirement is similar whether the supply voltage is generated on-chip or off-chip, as long as a large amount of off-chip decap is used and connected to the board ground. If the supply voltage is generated on-chip, the regulator needs to be carefully designed against ESD induced noise. In addition, the rail clamp, if not optimized, deteriorates the power integrity with its instability. The ESD-induced supply fluctuation may cause latch-up without careful attention to the well-bias scheme