Fault-tolerant computer study

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed

Monitor amb control strategies to reduce the impact of process variations in digital circuits

As CMOS technology scales down, Process, Voltage, Temperature and Ageing (PVTA) variations have an increasing impact on the performance and power consumption of electronic devices. These issues may hold back the continuous improvement of these devices in the near future. There are several ways to face the variability problem: to increase the operating margins of maximum clock frequency, the implementation of lithographic friendly layout styles, and the last one and the focus of this thesis, to adapt the circuit to its actual manufacturing and environment conditions by tuning some of the adjustable parameters once the circuit has been manufactured. The main challenge of this thesis is to develop a low-area variability compensation mechanism to automatically mitigate PVTA variations in run-time, i.e. while integrated circuit is running. This implies the development of a sensor to obtain the most accurate picture of variability, and the implementation of a control block to knob some of the electrical parameters of the circuit.A mesura que la tecnologia CMOS escala, les variacions de Procés, Voltatge, Temperatura i Envelliment (PVTA) tenen un impacte creixent en el rendiment i el consum de potència dels dispositius electrònics. Aquesta problemàtica podria arribar a frenar la millora contínua d'aquests dispositius en un futur proper. Hi ha diverses maneres d'afrontar el problema de la variabilitat: relaxar el marge de la freqüència màxima d'operació, implementar dissenys físics de xips més fàcils de litografiar, i per últim i com a tema principal d'aquesta tesi, adaptar el xip a les condicions de fabricació i d'entorn mitjançant la modificació d'algun dels seus paràmetres ajustables una vegada el circuit ja ha estat fabricat. El principal repte d'aquesta tesi és desenvolupar un mecanisme de compensació de variabilitat per tal de mitigar les variacions PVTA de manera automàtica en temps d'execució, és a dir, mentre el xip està funcionant. Això implica el desenvolupament d'un sensor capaç de mesurar la variabilitat de la manera més acurada possible, i la implementació d'un bloc de control que permeti l'ajust d'alguns dels paràmetres elèctrics dels circuits

IC design for reliability

textAs the feature size of integrated circuits goes down to the nanometer scale, transient and permanent reliability issues are becoming a significant concern for circuit designers. Traditionally, the reliability issues were mostly handled at the device level as a device engineering problem. However, the increasing severity of reliability challenges and higher error rates due to transient upsets favor higher-level design for reliability (DFR). In this work, we develop several methods for DFR at the circuit level. A major source of transient errors is the single event upset (SEU). SEUs are caused by high-energy particles present in the cosmic rays or emitted by radioactive contaminants in the chip packaging materials. When these particles hit a N+/P+ depletion region of an MOS transistor, they may generate a temporary logic fault. Depending on where the MOS transistor is located and what state the circuit is at, an SEU may result in a circuit-level error. We analyze SEUs both in combinational logic and memories (SRAM). For combinational logic circuit, we propose FASER, a Fast Analysis tool of Soft ERror susceptibility for cell-based designs. The efficiency of FASER is achieved through its static and vector-less nature. In order to evaluate the impact of SEU on SRAM, a theory for estimating dynamic noise margins is developed analytically. The results allow predicting the transient error susceptibility of an SRAM cell using a closedform expression. Among the many permanent failure mechanisms that include time-dependent oxide breakdown (TDDB), electro-migration (EM), hot carrier effect (HCE), and negative bias temperature instability (NBTI), NBTI has recently become important. Therefore, the main focus of our work is NBTI. NBTI occurs when the gate of PMOS is negatively biased. The voltage stress across the gate generates interface traps, which degrade the threshold voltage of PMOS. The degraded PMOS may eventually fail to meet timing requirement and cause functional errors. NBTI becomes severe at elevated temperatures. In this dissertation, we propose a NBTI degradation model that takes into account the temperature variation on the chip and gives the accurate estimation of the degraded threshold voltage. In order to account for the degradation of devices, traditional design methods add guard-bands to ensure that the circuit will function properly during its lifetime. However, the worst-case based guard-bands lead to significant penalty in performance. In this dissertation, we propose an effective macromodel-based reliability tracking and management framework, based on a hybrid network of on-chip sensors, consisting of temperature sensors and ring oscillators. The model is concerned specifically with NBTIinduced transistor aging. The key feature of our work, in contrast to the traditional tracking techniques that rely solely on direct measurement of the increase of threshold voltage or circuit delay, is an explicit macromodel which maps operating temperature to circuit degradation (the increase of circuit delay). The macromodel allows for costeffective tracking of reliability using temperature sensors and is also essential for enabling the control loop of the reliability management system. The developed methods improve the over-conservatism of the device-level, worstcase reliability estimation techniques. As the severity of reliability challenges continue to grow with technology scaling, it will become more important for circuit designers/CAD tools to be equipped with the developed methods.Electrical and Computer Engineerin

Recent Trends in Communication Networks

In recent years there has been many developments in communication technology. This has greatly enhanced the computing power of small handheld resource-constrained mobile devices. Different generations of communication technology have evolved. This had led to new research for communication of large volumes of data in different transmission media and the design of different communication protocols. Another direction of research concerns the secure and error-free communication between the sender and receiver despite the risk of the presence of an eavesdropper. For the communication requirement of a huge amount of multimedia streaming data, a lot of research has been carried out in the design of proper overlay networks. The book addresses new research techniques that have evolved to handle these challenges

Soundings of the ionospheric HF radio link between Antarctica and Spain

Aquest treball ha estat realitzat sota el context del projecte Antàrtic del Grup d’Investigació en Electromagnetisme i Comunicacions de La Salle (Universitat Ramon Llull). L’objectiu d’aquest projecte és l’estudi del canal ionosfèric com a canal de comunicacions digitals i el disseny de modulacions avançades adaptades. Aquest treball de tesi es centra en el sondeig del canal HF al llarg de tres campanyes consecutives des de 2009 fins 2012 entre la Base Antártica Española (BAE) i l’Observatorio de l’Ebre (OE). En primer lloc, a partir del sondeig en banda estreta s’han obtingut la disponibilitat i la freqüència de màxima disponibilitat (FLA) entre la BAE i OE en el període 2009-2012. En segon lloc, el sondeig en banda ampla ens ha permès estimar la relació senyal-soroll en banda ampla, la dispersió temporal (composite multipath spread), la dispersió freqüencial (composite Doppler spread and Doppler frequency shift) i el temps de propagació. En tercer lloc, s’ha investigat la variació intra-diària i inter-diària d’alguns paràmetres (Densitat total d’electrons, freqüències crítiques i la MUF3000) que han estat mesurades en sondeig vertical en quatre estacions situades al llarg del camí entre la BAE i OE. Finalment, s’ha estudiat la correlació entre la FLA de l’enllaç oblic i la MUF300 de les estacions intermèdies properes als punts de reflexió.Este trabajo ha sido realizado en el contexto del proyecto Antártico del Grupo de Investigación en Electromagnetismo y Comunicaciones de La Salle (Universidad Ramon Llull). El objetivo de este proyecto es el estudio del canal ionosférico como canal de comunicaciones digitales además del diseño de modulaciones avanzadas adaptadas. Este trabajo se centra en el sondeo del canal HF a lo largo de tres campañas consecutivas desde 2009 hasta 2012 entre la Base Antártica Española (BAE) y el Observatorio del Ebro (OE). Primero, a partir del sondeo en banda estrecha se han obtenido la disponibilidad y la frecuencia de máxima disponibilidad (FLA) entre la BAE y OE en el periodo 2009-2012. En segundo lugar, el sondeo en banda ancha nos ha permitido estimar la relación señal-ruido en banda ancha, la dispersión temporal (composite multipath spread), la dispersión frecuencial (composite Doppler spread and Doppler frequency shift) y el tiempo de propagación. En tercer lugar, se ha investigado la variación intra-diaria y la inter-diaria de varios parámetros (Densidad total de electrones, frecuencias críticas y la MUF3000) que han sido medidas en sondeo vertical en cuatro estaciones situadas a lo largo del camino entre la BAE y OE.Finalmente, se ha estudiado la correlación entre la FLA del enlace oblicuo y la MUF300 de las estaciones intermedias cercanas a los puntos de reflexión.This work has been done in the context of the Antarctic Project of the Research Group in Electromagnetism and Communications of La Salle (Ramon Llull University). The aim of this project is to study the ionospheric channel as a digital communications channel as well as to design specific advanced modulations specially adapted to it. This work is devoted to the HF channel sounding throughout three consecutive surveys from 2009 to 2012 between the Spanish Antarctic Station (SAS) and the Ebro Observatory (OE). First, the availability and the Frequency of Largest Availability (FLA) of the SAS-OE link have been obtained from the narrowband sounding technique from 2009 to 2012. Second, wideband sounding of the SAS-OE link has been done to estimate the wideband Signal to Noise Ratio (SNR), the time dispersion (composite multipath spread), frequency dispersion (composite Doppler spread and Doppler frequency shift), and the propagation time. Third, there has been an investigation about the day-to-day and inter-day variations of various parameters (e.g., Total Electron Density, critical frequencies, and Maximum Usable Frequency for ground distance MUF(3000)) that have been measured at four Vertical Incidence Sounding (VIS) stations located over the SAS-OE link path throughout three consecutive surveys (from 2009 to 2012). Finally, the correlation between the FLA of the SAS-OE ionospheric link and the MUF(3000) obtained from VIS stations located close to the reflection points of the same link has been studied

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Temporary Assistance for Needy Families policy manual

This policy manual gives details of SNAP in South Carolina

Failures caused by supply fluctuations during system-level ESD

It is necessary to design robust electronic systems against system-level electrostatic discharge (ESD). In additional to withstanding ESD without hard failures (permanent damage), it is important that the system is robust against soft failures (recoverable loss of function or data), which can be caused by ESD-induced noise on signal inputs and power nets. Besides radiation, the current injection into the circuit alone can cause these disturbances, especially the sharp current spike of a high amplitude in system-level ESD. The waveform of this current is similar in various ESD test setups. Circuit models with distributed elements enable accurate modeling of the system-level ESD current in contact discharge. Experiments have shown that ESD-induced noise on signal traces starts to disturb the IO input at very low ESD levels, and the effectiveness of the transient voltage suppressor (TVS) on board is limited. The noise on supply is global to integrated circuit (IC), as it travels across all the power domains. The waveform of the noise depends on the polarity of the ESD current and the type of ESD protection. The experiments have shown that the supply fluctuation can be quite severe, as a strong reverse of the on-chip supply is indicated by monitor circuits starting from the ESD levels below the common required passing level. This poses a requirement of a minimum amount of on-chip decoupling capacitances (decaps) to limit the amplitude of supply fluctuations. This requirement is similar whether the supply voltage is generated on-chip or off-chip, as long as a large amount of off-chip decap is used and connected to the board ground. If the supply voltage is generated on-chip, the regulator needs to be carefully designed against ESD induced noise. In addition, the rail clamp, if not optimized, deteriorates the power integrity with its instability. The ESD-induced supply fluctuation may cause latch-up without careful attention to the well-bias scheme