ECCCII-Based Current-Mode Universal Filter with Orthogonal Control of w_o and Q

This paper presents a new current-mode current-controlled four-input five-output universal filter employing one current-controlled current conveyor (CCCII), one electronically tunable CCCII and two grounded capacitors. The proposed configuration provides lowpass, bandpass, highpass, bandstop and allpass current responses that taken from the high-output impedance terminals, which enable easy cascadability of the current-mode operation. The filter also offers both orthogonal and electronic controls of the natural frequency and the quality factor through adjusting the bias current of the CCCIIs. For realizing all the filter responses, the proposed filter does not require passive component-matching condition and both active and passive sensitivities are low. In addition, a new current-mode current-controlled single-input five-output universal filter can be achieved by using an additional multiple-output minus-type CCCII. The proposed filter is simulated using PSPICE simulations to confirm the theoretical analysis

Automatic tuning for linearly tunable filter

A new tuning scheme for linearly tunable high-Q filters is proposed. The tuning method is based on using the phase information for both frequency and Q factor tuning. There is no need to find out the relationship between a filter's passband magnitude and Q. A gm-C biquadratic filter is designed to demonstrate the proposed tuning circuitry. The project includes a phase locked loop (PLL) based frequency tuning loop, reference clock generator, and differential difference amplifier (DDA) for dealing with frequency and Q factor tuning loop and linearly tunable second order gm-C bandpass filter. Simulation results for a 10 MHz prototype filter using AMI 0.5μm process is presented. The chip testing results show that the automatic frequency tuning error is 2.5% for the 10 MHz case

Unconventional Circuit Elements for Ladder Filter Design

Kmitočtové filtry jsou lineární elektrické obvody, které jsou využívány v různých oblastech elektroniky. Současně tvoří základní stavební bloky pro analogové zpracování signálů. V poslední dekádě bylo zavedeno množství aktivních stavebních bloků pro analogové zpracování signálů. Stále však existuje potřeba vývoje nových aktivních součástek, které by poskytovaly nové možnosti a lepší parametry. V práci jsou diskutovány různé aspekty obvodů pracujících v napěťovém, proudovém a smíšném módu. Práce reaguje na dnešní potřebu nízkovýkonových a nízkonapěťových aplikací pro přenosné přístroje a mobilní komunikační systémy a na problémy jejich návrhu. Potřeba těchto výkonných nízkonapěťových zařízení je výzvou návrhářů k hledání nových obvodových topologií a nových nízkonapěťových technik. V práci je popsána řada aktivních prvků, jako například operační transkonduktanční zesilovač (OTA), proudový konvejor II. generace (CCII) a CDTA (Current Differencing Transconductance Amplifier). Dále jsou navrženy nové prvky, jako jsou VDTA (Voltage Differencing Transconductance Amplifier) a VDVTA (Voltage Differencing Voltage Transconductance Amplifier). Všechny tyto prvky byly rovněž implementovány pomocí "bulk-driven" techniky CMOS s cílem realizace nízkonapěťových aplikací. Tato práce je rovněž zaměřena na náhrady klasických induktorů syntetickými induktory v pasivních LC příčkových filtrech. Tyto náhrady pak mohou vést k syntéze aktivních filtrů se zajímavými vlastnostmi.Frequency filters are linear electric circuits that are used in wide area of electronics. They are also the basic building blocks in analogue signal processing. In the last decade, a huge number of active building blocks for analogue signal processing was introduced. However, there is still the need to develop new active elements that offer new possibilities and better parameters. The current-, voltage-, or mixed-mode analog circuits and their various aspects are discussed in the thesis. This work reflects the trend of low-power (LP) low-voltage (LV) circuits for portable electronic and mobile communication systems and the problems of their design. The need for high-performance LV circuits encourages the analog designers to look for new circuit architectures and new LV techniques. This thesis presents various active elements such as Operational Transconductance Amplifier (OTA), Current Conveyor of Second Generation (CCII), and Current Differencing Transconductance Amplifier (CDTA), and introduces novel ones, such as Voltage Differencing Transconductance Amplifier (VDTA) and Voltage Differencing Voltage Transconductance Amplifier (VDVTA). All the above active elements were also designed in CMOS bulk-driven technology for LP LV applications. This thesis is also focused on replacement of conventional inductors by synthetic ones in passive LC ladder filters. These replacements can lead to the synthesis of active filters with interesting parameters.

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

High performance continuous-time filters for information transfer systems

Vast attention has been paid to active continuous-time filters over the years. Thus as the cheap, readily available integrated circuit OpAmps replaced their discrete circuit versions, it became feasible to consider active-RC filter circuits using large numbers of OpAmps. Similarly the development of integrated operational transconductance amplifier (OTA) led to new filter configurations. This gave rise to OTA-C filters, using only active devices and capacitors, making it more suitable for integration. The demands on filter circuits have become ever more stringent as the world of electronics and communications has advanced. In addition, the continuing increase in the operating frequencies of modern circuits and systems increases the need for active filters that can perform at these higher frequencies; an area where the LC active filter emerges. What mainly limits the performance of an analog circuit are the non-idealities of the used building blocks and the circuit architecture. This research concentrates on the design issues of high frequency continuous-time integrated filters. Several novel circuit building blocks are introduced. A novel pseudo-differential fully balanced fully symmetric CMOS OTA architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. On the level of system architectures, a novel filter low-voltage 4th order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled-inductors, thus providing bandwidth tuning with small passband ripple. As part of a direct conversion dual-mode 802.11b/Bluetooth receiver, a BiCMOS 5th order low-pass channel selection filter is designed. The filter operated from a single 2.5V supply and achieves a 76dB of out-of-band SFDR. A digital automatic tuning system is also implemented to account for process and temperature variations. As part of a Bluetooth transmitter, a low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications

A digital tuning scheme for digitally programmable integrated continuous-time filters and techniques for high-precision monolithic linear circuit design and implementation

Multiple topics which all focus on precision monolithic circuit design but beyond this are not directly related to each other are presented. The first topic is a digital tuning scheme for digitally programmable integrated continuous-time filters (4), (8) - (10). Emphasis of this research is on development of a more general tuning scheme which can be applicable to various filter functions as well as high-frequency applications. The tuning scheme consists of two phases: system identification and adjustment. Various continuous-time filter identification methods including time-domain and frequency-domain approaches are investigated, and a filter adjustment algorithm is presented. Potential of high accuracy of the proposed tuning scheme and successful applicability to high-frequency filters with versatile functions have been demonstrated through simulations and experiments;Four other topics are separately presented. First, nonidealities associated with high-precision amplifiers (5), (7) are discussed. Special emphasis is given on analysis of statistical characteristics of random CMRR and offset of CMOS op-amps which can help estimating yield of high-volume production and help engineers design for a given yield. Next, an automatic offset compensation scheme for CMOS op-amps with ping-pong control (2), (6) is presented. A very low-voltage circuit design technique using floating gate MOSFETs (3) is introduced. Finally, an accurate and matching-free threshold voltage extraction scheme using a ratio-independent SC amplifier and a dynamic current mirror (1) is discussed

A wide dynamic range high-q high-frequency bandpass filter with an automatic quality factor tuning scheme

An 80 MHz bandpass filter with a tunable quality factor of 16∼44 using an improved transconductor circuit is presented. A noise optimized biquad structure for high-Q, high- frequency bandpass filter is proposed. The quality factor of the filter is tuned using a new quality factor locked loop algorithm. It was shown that a second-order quality factor locked loop is necessary and sufficient to tune the quality factor of a bandpass filter with zero steady state error. The accuracy, mismatch, and sensitivty analysis of the new tuning scheme was performed and analyzed. Based on the proposed noise optimized filter structure and new quality factor tuning scheme, a biquad filter was designed and fabricated in 0.25 μm BiCMOS process. The measured results show that the biquad filter achieves a SNR of 45 dB at IMD of 40 dB. The P-1dB compression point and IIP3 of the filter are -10 dBm and -2.68 dBm, respectively. The proposed biquad filter and quality factor tuning scheme consumes 58mW and 13 mW of power at 3.3 V supply.Ph.D.Committee Chair: Allen Phillip; Committee Member: Hasler Paul; Committee Member: Keezer David; Committee Member: Kenny James; Committee Member: Pan Ronghu