Novel TCAD oriented definition of the off-state breakdown voltage in Schottky-gate FETs: a 4H SiC MESFET case study

Physics-based breakdown voltage optimization in Schottky-barrier power RF and microwave field-effect transistors as well as in high-speed power-switching diodes is today an important topic in technology computer-aided design (TCAD). OFF-state breakdown threshold criteria based on the magnitude of the Schottky-barrier leakage current can be directly applied to TCAD; however, the results obtained are not accurate due to the large uncertainty in the Schottky-barrier parameters and models arising above all in advanced wide-gap semiconductors and to the need of performing high-temperature simulations to improve the numerical convergence of the model. In this paper, we suggest a novel OFF-state breakdown criterion, based on monitoring the magnitude (at the drain edge of the gate) of the electric field component parallel to the current density. The new condition is shown to be consistent with more conventional definitions and to exhibit a significantly reduced sensitivity with respect to physical parameter variation

Impact of buffer charge on the reliability of carbon doped AlGaN/GaN-on-Si HEMTs

Charge trapping and transport in the carbon doped GaN buffer of an AlGaN/GaN-on-Si HEMT have been investigated. Back-gating and dynamic RON experiments show how the onset of leakage in the strain relief layer at a lower field than that through the upper part of the structure can result in serious long-term trapping leading to current collapse under standard device operating conditions. Controlling current-collapse requires control of not only the layer structures and its doping, but also the precise balance of leakage in each layer

Advanced AlGaN/GaN HEMT technology, design, fabrication and characterization

Nowadays, the microelectronics technology is based on the mature and very well established silicon (Si) technology. However, Si exhibits some important limitations regarding its voltage blocking capability, operation temperature and switching frequency. In this sense, Gallium Nitride (GaN)-based high electron mobility transistors (HEMTs) devices have the potential to make this change possible. The unique combination of the high-breakdown field, the high-channel electron mobility of the two dimensional electron gas (2DEG), and high-temperature of operation has attracted enormous interest from social, academia and industry and in this context this PhD dissertation has been made. This thesis has focused on improving the device performance through the advanced design, fabrication and characterization of AlGaN/GaN HEMTs, primarily grown on Si templates. The first milestone of this PhD dissertation has been the establishment of a know-how on GaN HEMT technology from several points of view: the device design, the device modeling, the process fabrication and the advanced characterization primarily using devices fabricated at Centre de Recherche sur l'Hétéro-Epitaxie (CRHEA-CNRS) (France) in the framework of a collaborative project. In this project, the main workhorse of this dissertation was the explorative analysis performed on the AlGaN/GaN HEMTs by innovative electrical and physical characterization methods. A relevant objective of this thesis was also to merge the nanotechnology approach with the conventional characterization techniques at the device scale to understand the device performance. A number of physical characterization techniques have been imaginatively used during this PhD determine the main physical parameters of our devices such as the morphology, the composition, the threading dislocations density, the nanoscale conductive pattern and others. The conductive atomic force microscopy (CAFM) tool have been widely described and used to understand the conduction mechanisms through the AlGaN/GaN Ohmic contact by performing simultaneously topography and electrical conductivity measurements. As it occurs with the most of the electronic switches, the gate stack is maybe the critical part of the device in terms of performance and longtime reliability. For this reason, how the AlGaN/GaN HEMT gate contact affects the overall HEMT behaviour by means of advanced characterization and modeling has been intensively investigated. It is worth mentioning that the high-temperature characterization is also a cornerstone of this PhD. It has been reported the elevated temperature impact on the forward and the reverse leakage currents for analogous Schottky gate HEMTs grown on different substrates: Si, sapphire and free-standing GaN (FS-GaN). The HEMT' forward-current temperature coefficients (T^a) as well as the thermal activation energies have been determined in the range of 25-300 ºC. Besides, the impact of the elevated temperature on the Ohmic and gate contacts has also been investigated. The main results of the gold-free AlGaN/GaN HEMTs high-voltage devices fabricated with a 4 inch Si CMOS compatible technology at the clean room of the CNM in the framework of the industrial contract with ON semiconductor were presented. We have shown that the fabricated devices are in the state-of-the-art (gold-free Ohmic and Schottky contacts) taking into account their power device figure-of-merit ((VB^2)/Ron) of 4.05×10^8 W/cm^2. Basically, two different families of AlGaN/GaN-on-Si MIS-HEMTs devices were fabricated on commercial 4 inch wafers: (i) using a thin ALD HfO2 (deposited on the CNM clean room) and (ii) thin in-situ grown Si3N4, as a gate insulator (grown by the vendor). The scientific impact of this PhD in terms of science indicators is of 17 journal papers (8 as first author) and 10 contributions at international conferences

GaN Power Devices: Discerning Application-Specific Challenges and Limitations in HEMTs

GaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is extended for low voltage devices ( \u3c 100 V), presenting results to optimize both lateral features and vertical features. For low voltage design, simulation work suggests that breakdown is more reliant on punch-through as the primary breakdown mechanism rather than on vertical leakage current as is the case with high-voltage devices. A fabrication process flow has been developed for fabricating Schottky-gate, and MIS-HEMT structures at UCF in the CREOL cleanroom. The fabricated devices were designed to validate the simulation work for low voltage GaN devices. The UCF fabrication process is done with a four layer mask, and consists of mesa isolation, ohmic recess etch, an optional gate insulator layer, ohmic metallization, and gate metallization. Following this work, the fabrication process was transferred to the National Nano Device Laboratories (NDL) in Hsinchu, Taiwan, to take advantage of the more advanced facilities there. Following fabrication, a study has been performed on defect induced performance degradation, leading to the observation of a new phenomenon: trap induced negative differential conductance (NDC). Typically NDC is caused by self-heating, however by implementing a substrate bias test in conjunction with pulsed I-V testing, the NDC seen in our fabricated devices has been confirmed to be from buffer traps that are a result of poor channel carrier confinement during the dc operating condition