Developed cascaded multilevel inverter topology to minimise the number of circuit devices and voltage stresses of switches

In this study, a novel structure for cascade multilevel inverter is presented. The proposed inverter can generate all possible DC voltage levels with the value of positive and negative. The proposed structure results in reduction of switches number, relevant gate driver circuits and also the installation area and inverter cost. The suggested inverter can be used as symmetric and asymmetric structures. Comparing the peak inverse voltage and losses of the proposed inverter with conventional multilevel inverters show the superiority of the proposed converter. The operation and good performance of the proposed multilevel inverter have been verified by the simulation results of a single-phase nine-level symmetric and 17-level asymmetric multilevel inverter and experimental results of a nine-level and 17-level inverters. Simulation and experimental results confirmed the validity and effectiveness performance of the proposed inverter

A New Symmetric/Asymmetric Multilevel Inverter Based on Cascaded Connection of Sub-Multilevel Units Aiming less Switching Components and Total Blocked Voltage

In this paper, a new multilevel inverter is designed to improve the power and voltage quality, which contains a lesser number of switches in the specified voltage levels. The proposed inverter includes power electronic devices such as switches and diode, and DC inputs. In the proposed structure the desired output voltage can be produced by considering a series connection of a novel sub-multilevel module. This structure can be designed in both the symmetric and asymmetric topologies. The proposed structure has superior condition in terms of semiconductor switches and drivers count as well as switching loss. Additionally, the Total Blocked Voltage (TBV) of the proposed converter is compared with the conventional and the novel converters. This topology is studied by symmetric as well as asymmetric topologies through simulations in Matlab/Simulink environment as well as experiments by a laboratory prototype

Design, Optimization and Implementation of a High Frequency Link Multilevel Cascaded Inverter

This thesis presents a new concept of cascaded MLI (CMLI) device reduction by utilizing low and high frequency transformer link. Two CMLI topologies, symmetric and asymmetric are proposed. Compared with counterpart CMLI topologies available in the literatures, the proposed two inverter topologies in this thesis have the advantages of utilizing least number of electronic components without compromising overall performance particularly when a high number of levels is required in the output voltage waveform

An Original Hybrid Multilevel DC-AC Converter Using Single-Double Source Unit for Medium Voltage Applications:Hardware Implementation and Investigation

In this article, an original hybrid multilevel DC-AC converter configurations are proposed by using single-double source unit for medium voltage applications. The proposed topologies are derived by hybridization of single and double source units with polarity changer and cascaded with full-bridge converter for medium and high voltage applications. Two different hybrid topologies presented and each topology configured for both symmetric and asymmetric method. The proposed hybrid topologies compared with the conventional cascaded H-bridge converter (CHB), and the best topologies recommended for medium voltage applications. The comparison in terms of the number of switches, gate driver circuits, maximum blocking voltage by switches and total peak inverse voltages of switches presented. The proposed topologies require a small installation area and low cost. The validity of the proposed hybrid converter structures is verified by simulation using MATLAB/Simulink and hardware results. The simulation and hardware results show a good agreement with the theoretical approach

A Review on Multilevel Inverter Topologies

In this paper, a brief review of the multilevel inverter (MLI) topologies is presented. The two-level Voltage Source Inverter (VSI) requires a suitable filter to produce sinusoidal output waveforms. The high-frequency switching and the PWM method are used to create output waveforms with the least amount of ripples. Due to the switching losses, the traditional two-level inverter has some restrictions when running at high frequencies. For addressing this problem, multilevel inverters (MLI) with lower switching frequencies and reduced total harmonic distortion (THD) are employed, eliminating the requirement for filters and bulky transformers. Furthermore, improved performance at the high switching frequency, higher power quality (near to pure sinusoidal), and fewer switching losses are just a few of the benefits of MLI inverters. However, each switch has to have its own gate driver for implementing MLI, which adds to the system's complexity. Therefore, reducing the number of switches of MLI is necessary. This paper presents a review of some of the different current topologies using a lower number of switches. Doi: 10.28991/ESJ-2022-06-01-014 Full Text: PD

Design and implementation of a novel three-phase cascaded half-bridge inverter

In this study, a new circuit topology of a three-phase half-bridge multilevel inverter (MLI) is proposed. The proposed MLI that consists of a cascaded half-bridge structure along with a modified full-bridge structure requires less number of dc-power supplies and power semiconductor devices, e.g. insulated gate bipolar transistors and diodes when compared with the existing MLI topologies, which significantly reduces the size and cost of the inverter. Two different structures: isolated and non-isolated dc-power supply-based three-phase half-bridge MLIs are investigated. A number of generalised methods are proposed to determine the magnitude of the input dc-power supplies that has a great impact on the number of levels of the output voltage waveform. To verify the feasibility of the proposed MLI topology, a scaled down laboratory prototype three-phase half-bridge MLI is developed and the experimental results are analysed and compared with the simulation results. Experimental and simulation results reveal the feasibility and excellent features of the proposed inverter system

Asymmetric Cascaded Multilevel Inverter with Unequal Dc Sources using SPWM and MSVPWM Topologies

This paper introduces the modeling design and simulation of seven and thirteen levels cascaded asymmetric multilevel inverter (MLI) with reduced number of switches.  MLI is the most efficient energy converters which are essentially appropriated for high power applications with decrease total harmonics distortion (THD). MLI doesn't only get high power in the output but it is also utilized in renewable energy resources such as fuel cells, wind and photovoltaic cells. This paper principally focuses on a hybrid cascaded MLI with two and three unequal dc supplies which decreases the number of semiconductor power switches. Sinusoidal PWM (SPWM) and modified space vector PWM (MSVPWM) techniques are used to improve an ac output with reduced THD. The gating pulses for seven and thirteen level hybrid cascaded converter using SPWM and MSVPWM techniques are introduced. The results of these proposed modulation strategies reduce the percentage magnitude of THD. The performance of the proposed SPWM and MSVPWM topologies are verified using seven and thirteen levels cascaded asymmetric MLI via simulink/matlab. Keywords: Sinusoidal Pulse Width Modulation (SPWM), Modified Space Vector Pulse Width Modulation (MSVPWM), Multilevel Inverter (MLI), Total Harmonics Distortion (THD)

A Flexible Rung Ladder Structured Multilevel Inverter

The tenet of the multilevel inverter (MLI) is a peculiar kind in the voltage source inverter (VSI) family, which offers a prudent solution to prevailing issues of conventional two levels VSI, higher dv/dt and harmonic distortion, through a staircase/stepped output voltage from multiple separate dc sources (SDCs). The incessant research effort in the last four decades has bestowed a host of MLI topologies with different concepts, structures, component requirements and application appropriateness. The main issue with the MLI structures is the objectionable component count while upping the number of levels in the output staircase waveform. This paper suggests a new MLI structure, a flexible rung ladder structured multilevel inverter (FRLSMLI), with a savvy to operate both in symmetrical and asymmetrical modes involving only fewer component counts. The proposed FRLSMLI is basically a ladder structured bridge (H-bridge with additional rungs) and the rungs comprise either source inclusion-bypass cell (SIBC) or four level creator cell (FLCC). The FRLSMLI can synthesize fifteen levels with three SDCs. The simulation and experimental results are projected to validate the viability of proposed MLI in real time applications