Green on-chip inductors in three-dimensional integrated circuits

This thesis focuses on the technique for the improvement of quality factor and inductance of the TSV inductors and then on the utilization of TSV inductors in various on-chip applications such as DC-DC converter and resonant clocking. Through-silicon-vias (TSVs) are the enabling technique for three-dimensional integrated circuits (3D ICs). However, their large area significantly reduces the benefits that can be obtained by 3D ICs. On the other hand, a major limiting factor for the implementation of many on-chip circuits such as DC-DC converters and resonant clocking is the large area overhead induced by spiral inductors. Several works have been proposed in the literature to make inductors out of idle TSVs. In this thesis, the technique to improve the quality factor and inductance is proposed and then discusses about two applications utilizing TSV inductors i.e., inductive DC-DC converters and LC resonant clocking. The TSV inductor performs inferior to spiral inductors due to its increases losses. Hence to improve the performance of the TSV inductor, the losses should be reduced. Inductive DC-DC converters become prominent for on-chip voltage conversion because of their high efficiency compared with other types of converters (e.g. linear and capacitive converters). On the other hand, to reduce on-chip power, LC resonant clocking has become an attractive option due to its same amplitude and phases compared to other resonant clocking methods such as standing wave and rotary wave. A major challenge for both applications is associated with the required inductor area. In this thesis, the effectiveness of such TSV inductors in addressing both challenges are demonstrated --Abstract, page iv

A double-sided, shield-less stave prototype for the ATLAS upgrade strip tracker for the high luminosity LHC

A detailed description of the integration structures for the barrel region of the silicon strips tracker of the ATLAS Phase-II upgrade for the upgrade of the Large Hadron Collider, the so-called High Luminosity LHC (HL-LHC), is presented. This paper focuses on one of the latest demonstrator prototypes recently assembled, with numerous unique features. It consists of a shortened, shield-less, and double sided stave, with two candidate power distributions implemented. Thermal and electrical performances of the prototype are presented, as well as a description of the assembly procedures and tools

Magnetics and GaN for Integrated CMOS Voltage Regulators

The increased use of DC-consuming electronics in many applications relevant to everyday life, necessitates significant improvements to power conversion and distribution methodologies. The surge in mobile electronics created a new power application space where high efficiency, size, and reduced complexity are critical, and at the same time, many computational tasks are relegated to centralized cloud computing centers, which consume significant amounts of energy. In both those application spaces, conversion and distribution efficiency improvements of even a few-% proves to be more and more challenging. A lot of research and development efforts target each source of loss, in an attempt to improve power electronics such that it serves the advances in other fields of electronics. Non-isolated DC-DC converters are essential in every electronics system, and improvements to efficiency, volume, weight and cost are of utmost interest. In particular, increasing the operation frequency and the conversion ratio of such converters serves the purposes of reducing the number or required conversion steps, reducing converter size, and increasing efficiency. The aforementioned improvements can be achieved by using superior technologies for the components of the converter, and by implementing higher level of integration than most present-day converters exhibit. In this work, Gallium Nitride (GaN) high electron mobility transistors (HEMT) are utilized as switches in a half-bridge buck converter topology, in conjunction with fine-line 180nm complementary metal oxide semiconductor (CMOS) driver circuitry. The circuits are integrated through a face-to-face bonding technique which results in significant reduction in interconnects parasitics and allows faster, more efficient operation. This work shows that the use of GaN transistors for the converter gives an efficiency headroom that allow pairing converters with state-of-the-art thin-film inductors with magnetic material, a task that is currently usually relegated to air-core inductors. In addition, a new "core-clad" structure for thin-film magnetic integrated inductors is presented for the use with fully integrated voltage regulators (IVRs). The core-clad topology combines aspects from the two popular inductor topologies (solenoid and cladded) to achieve higher inductance density and improved high frequency performance

Trough-silicon-via inductor: Is it real or just a fantasy?

Through-silicon-vias (TSVs) can potentially be used to implement inductors in three-dimensional (3D) integrated system for minimal footprint and large inductance. However, different from conventional 2D spiral inductor, TSV inductors are buried in lossy substrate, thus suffering from low quality factors. This thesis presents how various process and design parameters affect their performance. A few interesting phenomena that are unique to TSV inductors are observed. We then proposed a novel shield mechanism utilizing the micro-channel, a technique conventionally used for heat removal, to reduce the substrate loss. The technique increases the quality factor and inductance of the TSV inductor by up to 21x and 17x respectively. It enables us to implement TSV inductors of up to 38x smaller area and 33% higher quality factor, compared with spiral inductors of the same inductance. To the best of the authors\u27 knowledge, this is the very first in-depth study on TSV inductors. We hope our study shall point out a new and exciting research direction for 3D IC designers --Abstract, page iii

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

An On-chip PVT Resilient Short Time Measurement Technique

As the CMOS technology nodes continue to shrink, the challenges of developing manufacturing tests for integrated circuits become more difficult to address. To detect parametric faults of new generation of integrated circuits such as 3D ICs, on-chip short-time intervals have to be accurately measured. The accuracy of an on-chip time measurement module is heavily affected by Process, supply Voltage, and Temperature (PVT) variations. This work presents a new on-chip time measurement scheme where the undesired effects of PVT variations are attenuated significantly. To overcome the effects of PVT variations on short-time measurement, phase locking methodology is utilized to implement a robust Vernier delay line. A prototype Time-to-Digital Converter (TDC) has been fabricated using TSMC 0.180 µm CMOS technology and experimental measurements have been carried out to verify the performance parameters of the TDC. The measurement results indicate that the proposed solution reduces the effects of PVT variations by more than tenfold compared to a conventional on-chip TDC. A coarse-fine time interval measurement scheme which is resilient to the PVT variations is also proposed. In this approach, two Delay Locked Loops (DLLs) are utilized to minimize the effects of PVT on the measured time intervals. The proposed scheme has been implemented using CMOS 65nm technology. Simulation results using Advanced Design System (ADS) indicate that the measurement resolution varies by less than 0.1ps with ±15% variations of the supply voltage. The proposed method also presents a robust performance against process and temperature variations. The measurement accuracy changes by a maximum of 0.05ps from slow to fast corners. The implemented TDC presents a robust performance against temperature variations too and its measurement accuracy varies a few femto-seconds from -40 ºC to +100 ºC. The principle of robust short-time measurement was used in practice to design and implement a state-of-the-art Coordinate Measuring Machine (CMM) for an industry partner to measure geometrical features of transmission parts with micrometer resolution. The solution developed for the industry partner has resulted in a patent and a product in the market. The on-chip short-time measurement technology has also been utilized to develop a solution to detect Hardware Trojans

Integrated thin film magnetics in advanced organic substrates

This thesis investigates the challenges of integrating thin film magnetics into advanced organic substrates for Power Supply in Package (PwrSiP) applications. The surface conditions of the substrate on which the thin films were deposited was found to play a critical role in terms of the magnetic performance and efficacy of the material used as the magnetic passive component. Whence, planarization of the underlying substrate, or a release process with which the magnetic core could be deposited, and later liberated from a polymer layer spun on smooth Si were developed in order to address the issue of surface roughness of the underlying substrate. \newline\newline The released magnetic thin films were incorporated into advanced organic substrates by three methods, as follows: 1) the integration of the released magnetic core using wirebonds; 2) the embedding of the released magnetic material using a Flip-Chip approach; 3) fully embedding the released magnetic material between the prepreg layers in the PCB stack. \newline\newline Finally, methods for the modelling and characterisation of the magnetisation dynamics of thin film magnetics were developed. The modelling of the magnetisation dynamics comprises two approaches: 1) development of software which enables large scale numeric modelling of the magnetic thin films using graphical processing units; 2) development of analytical models to characterise the magnetisation dynamics of magnetic thin films. Both the analytic and numeric methods were developed in order to characterise the issue of surface roughness in magnetic thin films, which was found to result in severely degraded magnetic performance. Furthermore, the thickness dependent multimodal behaviour of amorphous CZTB films spanning thickness 80nm – 500nm were investigated using Brown’s continuous diffusion model of magnetic spins. It was found that there is a critical film thickness whereat there is a breakdown in the induced uniaxial anisotropy within the film, and hence, that thickness should be considered the maximum useful thickness of the material in ultra-low loss PwRSiP applications