Through-silicon-vias (TSVs) can potentially be used to implement inductors in three-dimensional (3D) integrated system for minimal footprint and large inductance. However, different from conventional 2D spiral inductor, TSV inductors are buried in lossy substrate, thus suffering from low quality factors. This thesis presents how various process and design parameters affect their performance. A few interesting phenomena that are unique to TSV inductors are observed. We then proposed a novel shield mechanism utilizing the micro-channel, a technique conventionally used for heat removal, to reduce the substrate loss. The technique increases the quality factor and inductance of the TSV inductor by up to 21x and 17x respectively. It enables us to implement TSV inductors of up to 38x smaller area and 33% higher quality factor, compared with spiral inductors of the same inductance. To the best of the authors\u27 knowledge, this is the very first in-depth study on TSV inductors. We hope our study shall point out a new and exciting research direction for 3D IC designers --Abstract, page iii
