Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

Analysis and design of ΣΔ Modulators for Radio Frequency Switchmode Power Amplifiers

Power amplifiers are an integral part of every basestation, macrocell, microcell and mobile phone, enabling data to be sent over the distances needed to reach the receiver’s antenna. While linear operation is needed for transmitting WCDMA and OFDM signals, linear operation of a power amplifier is characterized by low power efficiency, and contributes to unwanted power dissipation in a transmitter. Recently, a switchmode power amplifier operation was considered for reducing power losses in a RF transmitter. A linear and efficient operation of a PA can be achieved when the transmitted RF signal is ΣΔ modu- lated, and subsequently amplified by a nonlinear device. Although in theory this approach offers linearity and efficiency reaching 100%, the use of ΣΔ modulation for transmitting wideband signals causes problems in practical implementation: it requires high sampling rate by the digital hardware, which is needed for shaping large contents of a quantization noise induced by the modulator but also, the binary output from the modulator needs an RF power amplifier operating over very wide frequency band. This thesis addresses the problem of noise shaping in a ΣΔ modulator and nonlinear distortion caused by broadband operation in switchmode power amplifier driven by a ΣΔ modulated waveform. The problem of sampling rate increase in a ΣΔ modulator is solved by optimizing structure of the modulator, and subsequent processing of an input signal’s samples in parallel. Independent from the above, a novel technique for reducing quan- tization noise in a bandpass ΣΔ modulator using single bit quantizer is presented. The technique combines error pulse shaping and 3-level quantization for improving signal to noise ratio in a 2-level output. The improvement is achieved without the increase of a digital hardware’s sampling rate, which is advantageous also from the perspective of power consumption. The new method is explored in the course of analysis, and verified by simulated and experimental results. The process of RF signal conversion from the Cartesian to polar form is analyzed, and a signal modulator for a polar transmitter with a ΣΔ-digitized envelope signal is designed and implemented. The new modulator takes an advantage of bandpass digital to analog conversion for simplifying the analog part of the modulator. A deformation of the pulsed RF signal in the experimental modulator is demonstrated to have an effect primarily on amplitude of the RF signal, which is correctable with simple predistortion

Advanced digital modulation: Communication techniques and monolithic GaAs technology

Communications theory and practice are merged with state-of-the-art technology in IC fabrication, especially monolithic GaAs technology, to examine the general feasibility of a number of advanced technology digital transmission systems. Satellite-channel models with (1) superior throughput, perhaps 2 Gbps; (2) attractive weight and cost; and (3) high RF power and spectrum efficiency are discussed. Transmission techniques possessing reasonably simple architectures capable of monolithic fabrication at high speeds were surveyed. This included a review of amplitude/phase shift keying (APSK) techniques and the continuous-phase-modulation (CPM) methods, of which MSK represents the simplest case

Low-pass CMOS Sigma-Delta Converter

A crescente necessidade em dar-se uma melhor saúde à população obriga ao desenvolvimento de novos e melhores dispositivos médicos. Atualmente, uma área de desenvolvimento importante é a de dispositivos portáteis para análise de sinais biológicos, tais como o eletrocardiograma ou o electroencefalograma, ajudando os profissionais de saúde a fazer rápidos diagnósticos no terreno, ou mesmo para serem usados por cidadãos que necessitem de vigilância constante. O desenvolvimento destes aparelhos traz novos desafios para a comunidade cientifica, nomeadamente na interface analógico/digital, na qualidade dos dados obtidos e no gasto energético. Para se conceber um bom dispositivos médico é necessário um conversor analógico/digital para frequências baixas, com baixo consumo energético e elevada resolução. Esta dissertação começa por fornecer ao leitor a teoria básica sobre conversores analógico/digital (ADC) e estado de arte. Como principal objetivo do trabalho desenvolvido, é descrito o desenho de um ADC baseado numa arquitetura Sigma-Delta que vá de encontro aos requisitos mencionados. O conversor foi implementado numa tecnologia 130 nm CMOS, usando uma frequência de amostragem de 1 MHz, com uma largura de banda de 1 kHz e tensão de alimentação 1,2 V. É usada, nos integradores do sigma-delta, uma invulgar tipologia de Opamp de forma a obter um ganho elevado, sem recurso a técnicas cascode. O quantizador possui uma resolução de 1,5 bits e é realizado com dois comparadores dinâmicos, de forma a minimizar o consumo energético.The growing need to provide better health for the population requires the development of new and better medical devices. Portable devices for the analysis of biological signals, such as the electrocardiogram or electroencephalogram, is nowadays an important development, helping health professionals to come up with fast diagnoses on the field, or even for use by citizens who require constant vigilance . Developing these devices brings new challenges to the scientific community, namely at the analog/digital interface, the quality of data and power consumption. In order to design a good medical device it is necessary an analog/digital converter for low frequencies, with low power consumption and high resolution. This dissertation begins by providing the reader with the basic theory of analog/digital (ADC) and its state of the art. The main goal of the work is the design of an ADC based on a Sigma-Delta architecture that meets the necessary medical requirements. The converter was implemented in a 130 nm CMOS technology using a sampling frequency of 1 MHz, with a bandwidth of 1 kHz, and a source voltage of 1.2 V. The integrators of sigma-delta employs an unusual Opamp typology in order to reach a high gain, without resourcing to cascode techniques. The quantizer has a resolution of 1.5 bits and is realized with two dynamic comparators, in order to minimize power consumption

Fully-passive switched-capacitor techniques for high performance SAR ADC design

In recent years, SAR ADC becomes more and more popular in various low-power applications such as wireless sensors and low energy radios due to its circuit simplicity, high power efficiency, and scaling compatibility. However, its speed is limited by its successive approximation procedures and its power efficiency greatly reduces with the ADC resolution going beyond 10 bit. To address these issues, this thesis proposes to embed two techniques: 1) compressive sensing (CS) and 2) noise shaping (NS) to a conventional SAR ADC. The realization of both techniques are based on fully-passive switched-capacitor techniques. CS is a recently emerging sampling paradigm, stating that the sparsity of a signal can be exploited to reduce the ADC sampling rate below the Nyquist rate. Different from conventional CS frameworks which require dedicated analog CS encoders, this thesis proposes a fully-passive CS-SAR ADC architecture which only requires minor modification to a conventional SAR ADC. Two chips are fabricated in a 0.13 µm process to prove the concept. One chip is a single-channel CS-SAR ADC which can reduce the ADC conversion rate by 4 times, thus reducing the ADC power by 4 times. In many wireless sensing applications, multiple ADCs are commonly required to sense multi-channel signals such as multi-lead ECG sensing and parallel neural recording. Therefore, the other chip is a multi-channel CS-SAR ADC which can simultaneously convert 4-channel signals with a sampling rate of one channel’s Nyquist rate. At 0.8 V and 1 MS/s, both chips achieve an effective Walden FoM of around 5 fJ/conversion-step. This thesis also proposes a novel NS SAR ADC architecture that is simple, robust and low power for high-resolution applications. Compared to conventional ∆Σ ADCs, it replaces the power-hungry active integrator with a passive integrator which only requires one switch and two capacitors. Compared to previous 1st-order NS SAR ADC works, it achieves the best NS performance and can be easily extended to 2nd-order. A 1st-order 10-bit NS SAR ADC is fabricated in a 0.13 µm process. Through NS, SNDR increases by 6 dB with OSR doubled, achieving a 12- bit ENOB at OSR = 8. An improved version of a 2nd-order 9-bit NS SAR ADC is designed and simulated in a 40 nm process. The SNDR increases by 10 dB with OSR doubled, achieving a 14-bit ENOB at OSR = 16. At a bandwidth of 312.5 kHz, the Schreier FoM is 181 dB and the Walden FoM is 12.5 fJ/conversion-step, proving that the proposed NS SAR ADC architecture can achieve high resolution and high power efficiency simultaneously.Electrical and Computer Engineerin