Analysis and Design of Robust Multi-Gb/s Clock and Data Recovery Circuits

The bandwidth demands of modern computing systems have been continually increasing and the recent focus on parallel processing will only increase the demands placed on data communication circuits. As data rates enter the multi-Gb/s range, serial data communication architectures become attractive as compared to parallel architectures. Serial architectures have long been used in fibre optic systems for long-haul applications, however, in the past decade there has been a trend towards multi-Gb/s backplane interconnects. The integration of clock and data recovery (CDR) circuits into monolithic integrated circuits (ICs) is attractive as it improves performance and reduces the system cost, however it also introduces new challenges, one of which is robustness. In serial data communication systems the CDR circuit is responsible for recovering the data from an incoming data stream. In recent years there has been a great deal of research into integrating CDR circuits into monolithic ICs. Most research has focused on increasing the bandwidth of the circuits, however in order to integrate multi-Gb/s CDR circuits robustness, as well as performance, must be considered. In this thesis CDR circuits are analyzed with respect to their robustness. The phase detector is a critical block in a CDR circuit and its robustness will play a significant role in determining the overall performance in the presence of process non-idealities. Several phase detector architectures are analyzed to determine the effects of process non-idealities. Static phase offsets are introduced as a figure of merit for phase detectors and a mathematical framework is described to characterize the negative effects of static phase offsets on CDR circuits. Two approaches are taken to improve the robustness of CDR circuits. First, calibration circuits are introduced which correct for static phase offsets in CDR circuits. Secondly, phase detector circuits are introduced which have been designed to optimize both performance and robustness. Several prototype chips which implement these schemes will be described and measured results will be presented. These results show that while CDR circuits are vulnerable to the effects of process non-idealities, there are circuit techniques which can mitigate many of these concerns

Clock And Data Recovery Using Bang-bang Pll’s

Tez (Yüksek Lisans) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2008Thesis (M.Sc.) -- İstanbul Technical University, Institute of Science and Technology, 2008Bu çalışmada, saat ve data işaretlerinin yeniden çıkarımında kullanılan iki konumlu faz kititlemeli çevrimlerden bahsedilmiştir. Sistem seviyesinde hızlı simülasyonlar yapabilmek amacıyla çevrim elemanlarının davranışsal modelleri geliştirilmiştir. İki konumlu kontrol sistemlerinin el ile analizinin oldukça zor olmasından dolayı modelleme zorunlu hale gelmektedir. Ayrıca gerçeklenen elemanların idealsizliklerinden kaynaklanan davranışlar da olabilidiğince modellenmeye çalışılmıştır. Söz konusu faz kilitlemeli çevrimlerin sistem seviyesinde sağlaması gereken özelliklerin kabaca hesaplanması ve datadaki değişim sıklığının bu özellikleri nasıl etkilediği anlatılmıştır. Çevrim elemanlarının tranzistör seviyesinde nasıl gerçeklendiklerinden bahsedilmiştir. Çok kullanılan bir ring osilatör yapısı olan simetrik yüklü osilatör (Maneatis yük) çevrimde etkili bir şekilde kullanabilmek amacıyla modifiye edilmiştir. Osilatörün üretim ve sıcaklık değişimlerini tolere edebilmesi için kazancının yüksek olması gerekir. Bu da sistemin harici gürültü kaynaklarına (besleme, taban gürültüsü gibi) olan duyarlılığını oldukça arttırmaktadır. Bu nedenle osilatörü otomatik olarak kalibre eden bir teknik geliştirilmiştir. Değişik faz kilitlemeli çevrimlere uygulanabilen teknik için osilatörün akım kontollü olması gerekmektedir. Frekans kitlenmesi gerçekleştikten sonra osilatörün akımı bir analog-sayısal çevirici ile örneklenmekte ve asıl sistem bu nokta etrafında daha dar bir bölgede çalışmaktadır. Ayrıca, sıcaklıktan kaynaklanabilecek değişimler de analog-sayısal dönüştürücünün refererans akımı üzerinden kompanze edilmektedir. Son olarak, tasarlanan sistemin simülasyon sonuçları verilmiştir. 0.18um CMOS teknolojisinde tasarlanan devre 5Gb/s data hızlarında çalışabilmektedir.In this work, bang-bang PLL structures, which are extensively used in clock and data recovery systems, are investigated. Behavioral models of loop elements are created to do faster simulations in system level. This step is mandatory in bang-bang systems, which are hard to analyze with simple calculations. Some non-idealities of real circuit elements are inserted to these models. System level design issues of bang-bang PLL’s are discussed and the effect of data transition density to system specifications is mentioned. Transistor level implementations of loop elements are described. A popular delay cell with symmetric loads (Maneatis cell) is modified to be used effectively in a bang-bang loop. Gain of the VCO seems very large after initial design, which is required to cover the operating frequency range over process and temperature corners. Large gain makes the system prone to external noise sources such as noise from power supply, substrate etc. Therefore, an automatic calibration method is developed to reduce the VCO gain. This technique can be applied to any current controlled oscillators in various phase locked loops. After frequency lock is achieved, current of the oscillator is sampled by a current mode ADC and a narrower range is generated around that point. Additionally, frequency variation due to temperature is compensated through the specifically designed reference current of ADC. Finally, simulation results of CDR and calibration circuits are given. CDR is designed in 0.18um CMOS technology and can operate at 5Gb/s data rate.Yüksek LisansM.Sc

A Bang-Bang All-Digital PLL for Frequency Synthesis

abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time.Dissertation/ThesisM.S. Electrical Engineering 201

Design of clock and data recovery circuits for energy-efficient short-reach optical transceivers

Nowadays, the increasing demand for cloud based computing and social media services mandates higher throughput (at least 56 Gb/s per data lane with 400 Gb/s total capacity 1) for short reach optical links (with the reach typically less than 2 km) inside data centres. The immediate consequences are the huge and power hungry data centers. To address these issues the intra-data-center connectivity by means of optical links needs continuous upgrading. In recent years, the trend in the industry has shifted toward the use of more complex modulation formats like PAM4 due to its spectral efficiency over the traditional NRZ. Another advantage is the reduced number of channels count which is more cost-effective considering the required area and the I/O density. However employing PAM4 results in more complex transceivers circuitry due to the presence of multilevel transitions and reduced noise budget. In addition, providing higher speed while accommodating the stringent requirements of higher density and energy efficiency (< 5 pJ/bit), makes the design of the optical links more challenging and requires innovative design techniques both at the system and circuit level. This work presents the design of a Clock and Data Recovery Circuit (CDR) as one of the key building blocks for the transceiver modules used in such fibreoptic links. Capable of working with PAM4 signalling format, the new proposed CDR architecture targets data rates of 50−56 Gb/s while achieving the required energy efficiency (< 5 pJ/bit). At the system level, the design proposes a new PAM4 PD which provides a better trade-off in terms of bandwidth and systematic jitter generation in the CDR. By using a digital loop controller (DLC), the CDR gains considerable area reduction with flexibility to adjust the loop dynamics. At the circuit level it focuses on applying different circuit techniques to mitigate the circuit imperfections. It presents a wideband analog front end (AFE), suitable for a 56 Gb/s, 28-Gbaud PAM-4 signal, by using an 8x interleaved, master/ slave based sample and hold circuit. In addition, the AFE is equipped with a calibration scheme which corrects the errors associated with the sampling channels’ offset voltage and gain mismatches. The presented digital to phase converter (DPC) features a modified phase interpolator (PI), a new quadrature phase corrector (QPC) and multi-phase output with de-skewing capabilities.The DPC (as a standalone block) and the CDR (as the main focus of this work) were fabricated in 65-nm CMOS technology. Based on the measurements, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply. Although the CDR was not fully operational with the PAM4 input, the results from 25-Gbaud PAM2 (NRZ) test setup were used to estimate the performance. Under this scenario, the 1-UI JTOL bandwidth was measured to be 2 MHz with BER threshold of 10−4. The chip consumes 236 mW of power while operating on 1 − 1.2 V supply range achieving an energyefficiency of 4.27 pJ/bit

Circuit architectures for high speed CMOS clock and data recovery circuits

As semiconductor process technologies continue to scale and the demand for ubiquitous computing devices continues to grow with paradigms such as the internet of things (IOT), the availability of low-cost, low-power, high-speed and robust communication interfaces between these devices will be a major challenge that needs to be addressed. Even in traditional desktop computing devices, the off-chip bandwidth does not scale as fast as the on-chip bandwidth and has therefore been an important bottleneck to the growth in processing speed. Thus, intelligent techniques will have to be developed that allow the traditional lossy channels to be deployed at higher data rates, while minimizing cost and power, without paying much of a performance penalty. Over the last decade and a half, a great amount of research has been done to design monolithic transmitter and receiver integrated circuits (ICs) in silicon complementary metal-oxide semiconductor (CMOS) technology as opposed to traditional discrete SiGe, InP technologies owing to the low cost and ease of integration of CMOS technology. A key component of the receiver is the clock and data recovery (CDR) circuit, which extracts the clock from the incoming data stream and samples the data. The performance of the CDR is a major impediment to increasing data rates in a serial communication system. Several CDR architectures have been proposed to ensure that the performance is comparable to traditional discrete SiGe, InP devices. In this thesis, three different CDR circuit architectures are designed in a 180 nm CMOS process with a target data rate of 2 Gbps and compared in terms of performance, power and area. In order to provide a fair comparison, the corresponding channel and transmitter blocks are also designed and the entire serial communication link is simulated. The fundamentals of CDR circuit design are introduced and a complete guide to analysis and design of CDR circuits for high speed serial links is presented. The results of the comparison help to evaluate power, performance and area trade-offs during the design phase and to choose the right architecture for a given application

A 1.8-pJ/b, 12.5-25-Gb/s wide range all-digital clock and data recovery circuit

Recently, there has been a strong drive to replace established analog circuits for multi-gigabit clock and data recovery (CDR) by more digital solutions. We focused on phase locked loop-based all-digital CDR (AD-CDR) techniques which contain a digital loop filter (DLF) and a digital controlled oscillator (DCO) and pushed the digital integration up to a level where our DLF is entirely synthesized. To enable this, we found that extensive subsampling can be used to decrease the speed of the DLF while maintaining a good operation. Additionally, an Inverse Alexander phase detector and a 5.5-bit resolution DCO complete the AD-CDR architecture. As a result of the low complexity and digital architecture, the AD-CDR occupies a compact active chip area of 0.050 mm(2) and consumes only 46 mW at 25 Gb/s. This is the smallest area and the lowest power consumption compared with the state-of-the-art. In addition, our implementation is highly tunable due to the synthesized logic, and supports a wide operating range (12.5-25 Gb/s), which is a significantly larger range compared with the previous work. Finally, thanks to our digital architecture, the power dissipation decreases linearly while moving to the lower speeds of our operating range. This is in contrast with the most prior work, making our design truly adaptive

Design of a clock and data recovery circuit in 65 nm technology

As semiconductor fabrication technology develops, the demand for higher transmission data rates constantly increases; thus there is an urgent need for a power-efficient, robust and broad bandwidth chip-to-chip communication method. A lot of work has been done to address this issue as researchers strive for more integrated inter-IC communication technology with CMOS. A high-speed serial link (HSSL) can help meet this goal. The clock and data recovery circuit (CDR) is a critical component of the HSSL. CDR is built on the receiver end of the link after proper equalization. Its purpose is to extract clock signal which is not transmitted from the driver end and to use the extracted clock signal to sample the incoming data stream with optimal timing. In this thesis, the working mechanism of the CDR is described. A CDR consists of a phase detector, a charge pump, a loop filter and a voltage-controlled oscillator. This thesis includes an overview of all the building blocks of a PLL-based CDR, derivation of the mathematical formulations of the negative feedback loop, and a report on closed loop behavioral modeling of the entire CDR and implemented CDR building blocks at transistor level with TSMC 65 nm technology PDK with a 6.4 Gbps data rate. Also, this thesis provides a detailed noise analysis of the CDR. Lastly, some future work and possible design improvements are proposed

Design of a clock and data recovery circuit in 65 nm technology

As semiconductor fabrication technology develops, the demand for higher transmission data rates constantly increases; thus there is an urgent need for a power-efficient, robust and broad bandwidth chip-to-chip communication method. A lot of work has been done to address this issue as researchers strive for more integrated inter-IC communication technology with CMOS. A high-speed serial link (HSSL) can help meet this goal. The clock and data recovery circuit (CDR) is a critical component of the HSSL. CDR is built on the receiver end of the link after proper equalization. Its purpose is to extract clock signal which is not transmitted from the driver end and to use the extracted clock signal to sample the incoming data stream with optimal timing. In this thesis, the working mechanism of the CDR is described. A CDR consists of a phase detector, a charge pump, a loop filter and a voltage-controlled oscillator. This thesis includes an overview of all the building blocks of a PLL-based CDR, derivation of the mathematical formulations of the negative feedback loop, and a report on closed loop behavioral modeling of the entire CDR and implemented CDR building blocks at transistor level with TSMC 65 nm technology PDK with a 6.4 Gbps data rate. Also, this thesis provides a detailed noise analysis of the CDR. Lastly, some future work and possible design improvements are proposed

Design Techniques for High Performance Wireline Communication and Security Systems

As the amount of data traffic grows exponentially on the internet, towards thousands of exabytes by 2020, high performance and high efficiency communication and security solutions are constantly in high demand, calling for innovative solutions. Within server communication dominates todays network data transfer, outweighing between-server and server-to-user data transfer by an order of magnitude. Solutions for within-server communication tend to be very wideband, i.e. on the order of tens of gigahertz, equalizers are widely deployed to provide extended bandwidth at reasonable cost. However, using equalizers typically costs the available signal-to-noise ratio (SNR) at the receiver side. What is worse is that the SNR available at the channel becomes worse as data rate increases, making it harder to meet the tight constraint on error rate, delay, and power consumption. In this thesis, two equalization solutions that address optimal equalizer implementations are discussed. One is a low-power high-speed maximum likelihood sequence detection (MLSD) that achieves record energy efficiency, below 10 pico-Joule per bit. The other one is a phase-shaping equalizer design that suppresses inter-symbol interference at almost zero cost of SNR. The growing amount of communication use also challenges the design of security subsystems, and the emerging need for post-quantum security adds to the difficulties. Most of currently deployed cryptographic primitives rely on the hardness of discrete logarithms that could potentially be solved efficiently with a powerful enough quantum computer. Efficient post-quantum encryption solutions have become of substantial value. In this thesis a fast and efficient lattice encryption application-specific integrated circuit is presented that surpasses the energy efficiency of embedded processors by 4 orders of magnitude.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/146092/1/shisong_1.pd