Message sequence charts in the software engineering process

The software development process benefits from the use of Message Sequence Charts (MSC), which is a graphical language for displyaing the interaction behaviour of a system. We describe canonical applications of MSC independent of any software development methodology. We illustrate the use of MSC with a case study: the Meeting Scheduler

Message sequence chart specifications with cross verification

Current software specification verification methods are usually performed within the context of the specification method. There is little cross verification, pitting one type of specification against another, taking place. The most common techniques involve syntax checks across specifications or doing specification transformations and running verification within the new context. Since viewpoints of a system are different even within programming teams we concentrate on producing an efficient way to run cross verification on specifications, particularly specifications written with Message Sequence Charts and State Transition Diagrams.;In this work an algorithm is proposed in which all conditional MSCs are transformed into an algebraic representations, Message Flow Graphs and by stepwise refinement, a Global State Transition Graph is created. This GSTG has all the properties of a State Transition Diagram and therefore can be analyzed in conjunction with the original STD

TURTLE-P: a UML profile for the formal validation of critical and distributed systems

The timed UML and RT-LOTOS environment, or TURTLE for short, extends UML class and activity diagrams with composition and temporal operators. TURTLE is a real-time UML profile with a formal semantics expressed in RT-LOTOS. Further, it is supported by a formal validation toolkit. This paper introduces TURTLE-P, an extended profile no longer restricted to the abstract modeling of distributed systems. Indeed, TURTLE-P addresses the concrete descriptions of communication architectures, including quality of service parameters (delay, jitter, etc.). This new profile enables co-design of hardware and software components with extended UML component and deployment diagrams. Properties of these diagrams can be evaluated and/or validated thanks to the formal semantics given in RT-LOTOS. The application of TURTLE-P is illustrated with a telecommunication satellite system

Distributed Implementation of Message Sequence Charts

International audienc

Concurrent Specification and Timing Analysis of Digital Hardware using SDL (extended version)

Digital hardware is treated as a collection of interacting parallel components. This permits the use of a standard formal technique for specification and analysis of circuit designs. The ANISEED method (Analysis In SDL Enhancing Electronic Design) is presented for specifying and analysing timing characteristics of hardware designs using SDL (Specification and Description Language). A signal carries a binary value and an optional time-stamp. Components and circuit designs are instances of block types in library packages. The library contains specifications of typical components in single/multi-bit and untimed/timed forms. Timing may be specified at an abstract, behavioural or structural level. Timing properties are investigated using an SDL simulator or validator. Consistency of temporal and functional aspects may be assessed between designs at different levels of detail. Timing characteristics of a design may also be inferred from validator traces. A variety of examples is used, ranging from a simple gate specification to realistic examples drawn from a standard hardware verification benchmark

Automatic synthesis of SDL from MSC and its applications in forward and reverse engineering

Abstract Wider adoption of formal specification languages in industry is impeded by the lack of support for early development phases and for integration with older, legacy software. Methodology aimed at improving this situation is presented. The methodology uses Message Sequence Charts (MSC) as a "front-end" specification language and systematically applies an automatic synthesis technique to produce executable specifications in the telecommunications standard Specification and Description Language (SDL). Applications of the automatic synthesis technique for both forward and reverse engineering are demonstrated

Automatic test selection based on CEFSM specifications

Mutation analysis is a fault based testing method used initially for code based software testing. In this paper, this method is applied to formal specifications and used for automatic conformance test selection. This paper defines formally a set of mutation operators for CEFSM (Communicating Extended Finite State Machine) systems to enable the automated creation of mutant specifications. Mutants of a specification are used as selection criteria to pick out adequate test cases. Two different algorithms are proposed for the generation and selection of efficient test suites. Additionally, the operators and algorithms provide the basis of an automatic tool developed at the Budapest University of Technology and Economics. We present the results of an empirical study on the well-known INRES protocol acquired using the tool