Transient Safe Operating Area (tsoa) For Esd Applications

A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD). A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins. The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs. The methodology for output pins includes defining ESD design targets under Human Metal Model (HMM) type stress in high voltage Laterally Diffused MOS (LDMOS) outputs. First, the assessment of standalone LDMOS robustness is performed, followed by establishment of protection design guidelines. Secondly, standalone clamp HMM robustness is evaluated and a prediction methodology for HMM type stress is developed based on standardized testing. Finally, LDMOS and protection clamp parallel protection conditions are identifie

DEEP SUBMICRON CMOS VLSI CIRCUIT RELIABILITY MODELING, SIMULATION AND DESIGN

CMOS VLSI circuit reliability modeling and simulation have attracted intense research interest in the last two decades, and as a result almost all IC Design For Reliability (DFR) tools now try to incrementally simulate device wearout mechanisms in iterative ways. These DFR tools are capable of accurately characterizing the device wearout process and predicting its impact on circuit performance. Nevertheless, excessive simulation time and tedious parameter testing process often limit popularity of these tools in product design and fabrication. This work develops a new SPICE reliability simulation method that shifts the focus of reliability analysis from device wearout to circuit functionality. A set of accelerated lifetime models and failure equivalent circuit models are proposed for the most common MOSFET intrinsic wearout mechanisms, including Hot Carrier Injection (HCI), Time Dependent Dielectric Breakdown (TDDB), and Negative Bias Temperature Instability (NBTI). The accelerated lifetime models help to identify the most degraded transistors in a circuit in terms of the device's terminal voltage and current waveforms. Then corresponding failure equivalent circuit models are incorporated into the circuit to substitute these identified transistors. Finally, SPICE simulation is performed again to check circuit functionality and analyze the impact of device wearout on circuit operation. Device wearout effects are lumped into a very limited number of failure equivalent circuit model parameters, and circuit performance degradation and functionality are determined by the magnitude of these parameters. In this new method, it is unnecessary to perform a large number of small-step SPICE simulation iterations. Therefore, simulation time is obviously shortened in comparison to other tools. In addition, a reduced set of failure equivalent circuit model parameters, rather than a large number of device SPICE model parameters, need to be accurately characterized at each interim wearout process. Thus device testing and parameter extraction work are also significantly simplified. These advantages will allow circuit designers to perform quick and efficient circuit reliability analyses and to develop practical guidelines for reliable electronic designs

Dielectric reliability of copper/low-k interconnects

Ph.DDOCTOR OF PHILOSOPH

A Study of Nanometer Semiconductor Scaling Effects on Microelectronics Reliability

The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. This dissertation provides a methodology on how to accomplish this and provides techniques for deriving the expected product-level reliability on commercial memory products. Competing mechanism theory and the multiple failure mechanism model are applied to two separate experiments; scaled SRAM and SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope Beta=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and key parameters

Cross-Layer Resiliency Modeling and Optimization: A Device to Circuit Approach

The never ending demand for higher performance and lower power consumption pushes the VLSI industry to further scale the technology down. However, further downscaling of technology at nano-scale leads to major challenges. Reduced reliability is one of them, arising from multiple sources e.g. runtime variations, process variation, and transient errors. The objective of this thesis is to tackle unreliability with a cross layer approach from device up to circuit level

Prognostics and health management of power electronics

Prognostics and health management (PHM) is a major tool enabling systems to evaluate their reliability in real-time operation. Despite ground-breaking advances in most engineering and scientific disciplines during the past decades, reliability engineering has not seen significant breakthroughs or noticeable advances. Therefore, self-awareness of the embedded system is also often required in the sense that the system should be able to assess its own health state and failure records, and those of its main components, and take action appropriately. This thesis presents a radically new prognostics approach to reliable system design that will revolutionise complex power electronic systems with robust prognostics capability enhanced Insulated Gate Bipolar Transistors (IGBT) in applications where reliability is significantly challenging and critical. The IGBT is considered as one of the components that is mainly damaged in converters and experiences a number of failure mechanisms, such as bond wire lift off, die attached solder crack, loose gate control voltage, etc. The resulting effects mentioned are complex. For instance, solder crack growth results in increasing the IGBT’s thermal junction which becomes a source of heat turns to wire bond lift off. As a result, the indication of this failure can be seen often in increasing on-state resistance relating to the voltage drop between on-state collector-emitter. On the other hand, hot carrier injection is increased due to electrical stress. Additionally, IGBTs are components that mainly work under high stress, temperature and power consumptions due to the higher range of load that these devices need to switch. This accelerates the degradation mechanism in the power switches in discrete fashion till reaches failure state which fail after several hundred cycles. To this end, exploiting failure mechanism knowledge of IGBTs and identifying failure parameter indication are background information of developing failure model and prognostics algorithm to calculate remaining useful life (RUL) along with ±10% confidence bounds. A number of various prognostics models have been developed for forecasting time to failure of IGBTs and the performance of the presented estimation models has been evaluated based on two different evaluation metrics. The results show significant improvement in health monitoring capability for power switches.Furthermore, the reliability of the power switch was calculated and conducted to fully describe health state of the converter and reconfigure the control parameter using adaptive algorithm under degradation and load mission limitation. As a result, the life expectancy of devices has been increased. These all allow condition-monitoring facilities to minimise stress levels and predict future failure which greatly reduces the likelihood of power switch failures in the first place

Influence of Size and Interface Effects of Silicon Nanowire and Nanosheet for Ultra-Scaled Next Generation Transistors

Indiana University-Purdue University Indianapolis (IUPUI)In this work, we investigate the trade-off between scalability and reliability for next generation logic-transistors i.e. Gate-All-Around (GAA)-FET, Multi-Bridge-Channel (MBC)-FET. First, we analyze the electronic properties (i.e. bandgap and quantum conductance) of ultra-thin silicon (Si) channel i.e. nano-wire and nano-sheet based on first principle simulation. In addition, we study the influence of interface states (or dangling bonds) at Si-SiO2 interface. Second, we investigate the impact of bandgap change and interface states on GAA-FETs and MBC-FETs characteristics by employing Non-equilibrium Green's Function based device simulation. In addition to that we calculate the activation energy of Si-H bond dissociation at Si-SiO2 interface for different Si nano-wire/sheet thickness and different oxide electric- field. Utilizing these thickness dependent activation energies for corresponding oxide electric- field, in conjunction with reaction-diffusion model, we compute the characteristics shift and analyze the negative bias temperature instability in GAA-FET and MBC-FET. Based on our analysis, we estimate the operational voltage of these transistors for a life-time of 10 years and the ON current of the device at iso-OFF-current condition. For example, for channel length of 5 nm and thickness < 5 nm the safe operating voltage needs to be < 0.55V. Furthermore, our analysis suggests that the benefi t of Si thickness scaling can potentially be suppressed for obtaining a desired life-time of GAA-FET and MBC-FET

Experimental Characterization of Random Telegraph Noise and Hot Carrier Aging of Nano-scale MOSFETs

One of the emerging challenges in the scaling of MOSFETs is the reliability of ultra-thin gate dielectrics. Various sources can cause device aging, such as hot carrier aging (HCA), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and time dependent device breakdown (TDDB). Among them, hot carrier aging (HCA) has attracted much attention recently, because it is limiting the device lifetime. As the channel length of MOSFETs becomes smaller, the lateral electrical field increases and charge carriers become sufficiently energetic (“hot”) to cause damage to the device when they travel through the space charge region near the drain. Unlike aging that causes device parameters, such as threshold voltage, to drift in one direction, nano-scale devices also suffer from Random Telegraph Noise (RTN), where the current can fluctuate under fixed biases. RTN is caused by capturing/emitting charge carriers from/to the conduction channel. As the device sizes are reduced to the nano-meters, a single trap can cause substantial fluctuation in the current and threshold voltage. Although early works on HCA and RTN have improved the understanding, many issues remain unresolved and the aim of this project is to address these issues. The project is broadly divided into three parts: (i) an investigation on the HCA kinetics and how to predict HCA-induced device lifetime, (ii) a study of the interaction between HCA and RTN, and (iii) developing a new technique for directly measuring the RTN-induced jitter in the threshold voltage. To predict the device lifetime, a reliable aging kinetics is indispensable. Although early works show that HCA follows a power law, there are uncertainties in the extraction of the time exponent, making the prediction doubtful. A systematic experimental investigation was carried out in Chapter 4 and both the stress conditions and measurement parameters were carefully selected. It was found that the forward saturation current, commonly used in early work for monitoring HCA, leads to an overestimation of time exponents, because part of the damaged region is screened off by the space charges near the drain. Another source of errors comes from the inclusion of as-grown defects in the aging kinetics, which is not caused by aging. This leads to an underestimation of the time exponent. After correcting these errors, a reliable HCA kinetics is established and its predictive capability is demonstrated. There is confusion on how HCA and RTN interact and this is researched into in Chapter 5. The results show that for a device of average RTN, HCA only has a modest impact on RTN. RTN can either increase or decrease after HCA, depending on whether the local current under the RTN traps is rising or reducing. For a device of abnormally high RTN, RTN reduces substantially after HCA and the mechanism for this reduction is explored. The RTN-induced threshold voltage jitter, ∆Vth, is difficult to measure, as it is typically small and highly dynamic. Early works estimate this ∆Vth from the change in drain current and the accuracy of this estimation is not known. Chapter 6 focuses on developing a new ‘Trigger-When-Charged’ technique for directly measuring the RTN-induced ∆Vth. It will be shown that early works overestimate ∆Vth by a factor of two and the origin of this overestimation is investigated. This thesis consists of seven chapters. Chapter 1 introduces the project and its objectives. A literature review is given in Chapter 2. Chapter 3 covers the test facilities, measurement techniques, and devices used in this project. The main experimental results and analysis are given in Chapters 4-6, as described above. Finally, Chapter 7 concludes the project and discusses future works