Time-encoding analog-to-digital converters : bridging the analog gap to advanced digital CMOS? Part 2: architectures and circuits

The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs: they remain large in area and power consumption in spite of process scaling. Analog circuits based on time encoding [1], [2], where the signal information is encoded in the waveform transitions instead of its amplitude, have been developed to overcome these issues. While part one of this overview article [3] presented the basic principles of time encoding, this follow-up article describes and compares the main time-encoding architectures for analog-to-digital converters (ADCs) and discusses the corresponding design challenges of the circuit blocks. The focus is on structures that avoid, as much as possible, the use of traditional analog blocks like operational amplifiers (opamps) or comparators but instead use digital circuitry, ring oscillators, flip-flops, counters, an so on. Our overview of the state of the art will show that these circuits can achieve excellent performance. The obvious benefit of this highly digital approach to realizing analog functionality is that the resulting circuits are small in area and more compatible with CMOS process scaling. The approach also allows for the easy integration of these analog functions in systems on chip operating at "digital" supply voltages as low as 1V and lower. A large part of the design process can also be embedded in a standard digital synthesis flow

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Configurable 3D-integrated focal-plane sensor-processor array architecture

A mixed-signal Cellular Visual Microprocessor architecture with digital processors is described. An ASIC implementation is also demonstrated. The architecture is composed of a regular sensor readout circuit array, prepared for 3D face-to-face type integration, and one or several cascaded array of mainly identical (SIMD) processing elements. The individual array elements derived from the same general HDL description and could be of different in size, aspect ratio, and computing resources

High linearity analog and mixed-signal integrated circuit design

Linearity is one of the most important specifications in electrical circuits.;In Chapter 1, a ladder-based transconductance networks has been adopted first time to build a low distortion analog filters for low frequency applications. This new technique eliminated the limitation of the application with the traditional passive resistors for low frequency applications. Based on the understanding of this relationship, a strategy for designing high linear analog continuous-time filters has been developed. According to our strategy, a prototype analog integrated filter has been designed and fabricated with AMI05 0.5 um standard CMOS process. Experimental results proved this technique has the ability to provide excellent linearity with very limited active area.;In Chapter 2, the relationships between the transconductance networks and major circuit specifications have been explored. The analysis reveals the trade off between the silicon area saved by the transconductance networks and the some other important specifications such as linearity, noise level and the process variations of the overall circuit. Experimental results of discrete component circuit matched very well with our analytical outcomes to predict the change of linearity and noise performance associated with different transconductance networks.;The Chapter 3 contains the analysis and mathematical proves of the optimum passive area allocations for several most popular analog active filters. Because the total area is now manageable by the technique introduced in the Chapter 1, the further reduce of the total area will be very important and useful for efficient utilizing the silicon area, especially with the today\u27s fast growing area efficiency of the highly density digital circuits. This study presents the mathematical conclusion that the minimum passive area will be achieved with the equalized resistor and capacitor.;In the Chapter 4, a well recognized and highly honored current division circuit has been studied. Although it was claimed to be inherently linear and there are over 60 published works reported with high linearity based on this technique, our study discovered that this current division circuit can achieve, if proper circuit condition being managed, very limited linearity and all the experimental verified performance actually based on more general circuit principle. Besides its limitation, however, we invented a novel current division digital to analog converter (DAC) based on this technique. Benefiting from the simple circuit structure and moderate good linearity, a prototype 8-bit DAC was designed in TSMC018 0.2 um CMOS process and the post layout simulations exhibited the good linearity with very low power consumption and extreme small active area.;As the part of study of the output stage for the current division DAC discussed in the Chapter 4, a current mirror is expected to amplify the output current to drive the low resistive load. The strategy of achieving the optimum bandwidth of the cascode current mirror with fixed total current gain is discussed in the Chapter 5.;Improving the linearity of pipeline ADC has been the hottest and hardest topic in solid-state circuit community for decade. In the Chapter 6, a comprehensive study focus on the existing calibration algorithms for pipeline ADCs is presented. The benefits and limitations of different calibration algorithms have been discussed. Based on the understanding of those reported works, a new model-based calibration is delivered. The simulation results demonstrate that the model-based algorithms are vulnerable to the model accuracy and this weakness is very hard to be removed. From there, we predict the future developments of calibration algorithms that can break the linearity limitations for pipelined ADC. (Abstract shortened by UMI.

SiNAPS: An implantable active pixel sensor CMOS-probe for simultaneous large-scale neural recordings

Abstract Large-scale neural recordings with high spatial and temporal accuracy are instrumental to understand how the brain works. To this end, it is of key importance to develop probes that can be conveniently scaled up to a high number of recording channels. Despite recent achievements in complementary metal-oxide semiconductor (CMOS) multi-electrode arrays probes, in current circuit architectures an increase in the number of simultaneously recording channels would significantly increase the total chip area. A promising approach for overcoming this scaling issue consists in the use of the modular Active Pixel Sensor (APS) concept, in which a small front-end circuit is located beneath each electrode. However, this approach imposes challenging constraints on the area of the in-pixel circuit, power consumption and noise. Here, we present an APS CMOS-probe technology for Simultaneous Neural recording that successfully addresses all these issues for whole-array read-outs at 25 kHz/channel from up to 1024 electrode-pixels. To assess the circuit performances, we realized in a 0.18  μ m CMOS technology an implantable single-shaft probe with a regular array of 512 electrode-pixels with a pitch of 28  μ m. Extensive bench tests showed an in-pixel gain of 45.4 ± 0.4 dB (low pass, F-3 dB = 4 kHz), an input referred noise of 7.5 ± 0.67 μVRMS (300 Hz to 7.5 kHz) and a power consumptio

First order sigma-delta modulator of an oversampling ADC design in CMOS using floating gate MOSFETS

We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth