225 research outputs found
Analog Implementation of Fractional-Order Elements and Their Applications
With advancements in the theory of fractional calculus and also with widespread engineering application of fractional-order systems, analog implementation of fractional-order integrators and differentiators have received considerable attention. This is due to the fact that this powerful mathematical tool allows us to describe and model a real-world phenomenon more accurately than via classical āintegerā methods. Moreover, their additional degree of freedom allows researchers to design accurate and more robust systems that would be impractical or impossible to implement with conventional capacitors. Throughout this thesis, a wide range of problems associated with analog circuit design of fractional-order systems are covered: passive component optimization of resistive-capacitive and resistive-inductive type fractional-order elements, realization of active fractional-order capacitors (FOCs), analog implementation of fractional-order integrators, robust fractional-order proportional-integral control design, investigation of different materials for FOC fabrication having ultra-wide frequency band, low phase error, possible low- and high-frequency realization of fractional-order oscillators in analog domain, mathematical and experimental study of solid-state FOCs in series-, parallel- and interconnected circuit networks. Consequently, the proposed approaches in this thesis are important considerations in beyond the future studies of fractional dynamic systems
Spatio-temporal Learning with Arrays of Analog Nanosynapses
Emerging nanodevices such as resistive memories are being considered for
hardware realizations of a variety of artificial neural networks (ANNs),
including highly promising online variants of the learning approaches known as
reservoir computing (RC) and the extreme learning machine (ELM). We propose an
RC/ELM inspired learning system built with nanosynapses that performs both
on-chip projection and regression operations. To address time-dynamic tasks,
the hidden neurons of our system perform spatio-temporal integration and can be
further enhanced with variable sampling or multiple activation windows. We
detail the system and show its use in conjunction with a highly analog
nanosynapse device on a standard task with intrinsic timing dynamics- the TI-46
battery of spoken digits. The system achieves nearly perfect (99%) accuracy at
sufficient hidden layer size, which compares favorably with software results.
In addition, the model is extended to a larger dataset, the MNIST database of
handwritten digits. By translating the database into the time domain and using
variable integration windows, up to 95% classification accuracy is achieved. In
addition to an intrinsically low-power programming style, the proposed
architecture learns very quickly and can easily be converted into a spiking
system with negligible loss in performance- all features that confer
significant energy efficiency.Comment: 6 pages, 3 figures. Presented at 2017 IEEE/ACM Symposium on Nanoscale
architectures (NANOARCH
Symbolic Representation for Analog Realization of A Family of Fractional Order Controller Structures via Continued Fraction Expansion
This is the author accepted manuscript. The final version is available from Elsevier via the DOI in this record.This paper uses the Continued Fraction Expansion (CFE) method for analog realization of fractional order differ-integrator and few special classes of fractional order (FO) controllers viz. Fractional Order Proportional-Integral-Derivative (FOPID) controller, FO[PD] controller and FO lead-lag compensator. Contemporary researchers have given several formulations for rational approximation of fractional order elements. However, approximation of the controllers studied in this paper, due to having fractional power of a rational transfer function, is not available in analog domain; although its digital realization already exists. This motivates us for applying CFE based analog realization technique for complicated FO controller structures to get equivalent rational transfer functions in terms of the controller tuning parameters. The symbolic expressions for rationalized transfer function in terms of the controller tuning parameters are especially important as ready references, without the need of running CFE algorithm every time and also helps in the synthesis of analog circuits for such FO controllers
Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits
This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (Ī£Ī) modulators (Ī£ĪMs) analog-todigital converters (ADCs).
Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order Ī£ĪM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 Ī¼W, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB.
The final prototype circuit is a highly area and power efficient Ī£ĪM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuitās sensitivity to the circuit componentsā variations. This continuous-time, 2-1 MASH Ī£ĪM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The Ī£ĪM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the authorās knowledge the circuit achieves the lowest Walden FOMW for Ī£ĪMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date
Engineering Education and Research Using MATLAB
MATLAB is a software package used primarily in the field of engineering for signal processing, numerical data analysis, modeling, programming, simulation, and computer graphic visualization. In the last few years, it has become widely accepted as an efficient tool, and, therefore, its use has significantly increased in scientific communities and academic institutions. This book consists of 20 chapters presenting research works using MATLAB tools. Chapters include techniques for programming and developing Graphical User Interfaces (GUIs), dynamic systems, electric machines, signal and image processing, power electronics, mixed signal circuits, genetic programming, digital watermarking, control systems, time-series regression modeling, and artificial neural networks
A high-Q second-order all-pass delay network in CMOS
Analogue signal processing (ASP) is a promising alternative to DSP techniques in future telecommunication and dataĀ processingĀ solutions.Ā SecondāorderĀ allāpassĀ delayĀ networksĀ āĀ theĀ buildingĀ blocksĀ ofĀ ASPsĀ āĀ areĀ currentlyĀ primarilyĀ implemented in offāchip planar media, which is unsuited for volume production. In this work, a novel onāchip CMOS secondāorder allāpass network is proposed that includes a postāproduction tuning mechanism. It is shown that automated tuning with a genetic local optimizer can compensate for CMOS process variation and parasitics, which make physical realization otherwise infeasible. Measurements indicate a postātuning bandwidth of 280 MHz, peakātoānominal delay variation of 10 ns andĀ magnitudeĀ variationĀ ofĀ 3.1Ā dB.Ā ThisĀ isĀ theĀ firstĀ timeĀ thatĀ measurementĀ resultsĀ haveĀ beenĀ reportedĀ forĀ anĀ activeĀ inductorless onāchip secondāorder allāpass network with a delay Qāvalue larger than 1.http://digital-library.theiet.org/content/journals/iet-cdshj2018Electrical, Electronic and Computer Engineerin
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