MorphIC: A 65-nm 738k-Synapse/mm2^2 Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning

Recent trends in the field of neural network accelerators investigate weight quantization as a means to increase the resource- and power-efficiency of hardware devices. As full on-chip weight storage is necessary to avoid the high energy cost of off-chip memory accesses, memory reduction requirements for weight storage pushed toward the use of binary weights, which were demonstrated to have a limited accuracy reduction on many applications when quantization-aware training techniques are used. In parallel, spiking neural network (SNN) architectures are explored to further reduce power when processing sparse event-based data streams, while on-chip spike-based online learning appears as a key feature for applications constrained in power and resources during the training phase. However, designing power- and area-efficient spiking neural networks still requires the development of specific techniques in order to leverage on-chip online learning on binary weights without compromising the synapse density. In this work, we demonstrate MorphIC, a quad-core binary-weight digital neuromorphic processor embedding a stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning rule and a hierarchical routing fabric for large-scale chip interconnection. The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF) neurons and more than two million plastic synapses for an active silicon area of 2.86mm$^2$ in 65nm CMOS, achieving a high density of 738k synapses/mm$^2$. MorphIC demonstrates an order-of-magnitude improvement in the area-accuracy tradeoff on the MNIST classification task compared to previously-proposed SNNs, while having no penalty in the energy-accuracy tradeoff.Comment: This document is the paper as accepted for publication in the IEEE Transactions on Biomedical Circuits and Systems journal (2019), the fully-edited paper is available at https://ieeexplore.ieee.org/document/876400

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.

NASA Tech Briefs, Februrary 2013

Topics covered include: Measurements of Ultra-Stable Oscillator (USO) Allan Deviations in Space; Gaseous Nitrogen Orifice Mass Flow Calculator; Validation of Proposed Metrics for Two-Body Abrasion Scratch Test Analysis Standards; Rover Low Gain Antenna Qualification for Deep Space Thermal Environments; Automated, Ultra-Sterile Solid Sample Handling and Analysis on a Chip; Measuring and Estimating Normalized Contrast in Infrared Flash Thermography; Spectrally and Radiometrically Stable, Wideband, Onboard Calibration Source; High-Reliability Waveguide Vacuum/Pressure Window; Methods of Fabricating Scintillators With Radioisotopes for Beta Battery Applications; Magnetic Shield for Adiabatic Demagnetization Refrigerators (ADR); CMOS-Compatible SOI MESFETS for Radiation-Hardened DC-to-DC Converters; Silicon Heat Pipe Array; Adaptive Phase Delay Generator; High-Temperature, Lightweight, Self-Healing Ceramic Composites for Aircraft Engine Applications; Treatment to Control Adhesion of Silicone-Based Elastomers; High-Temperature Adhesives for Thermally Stable Aero-Assist Technologies; Rockballer Sample Acquisition Tool; Rock Gripper for Sampling, Mobility, Anchoring, and Manipulation; Advanced Magnetic Materials Methods and Numerical Models for Fluidization in Microgravity and Hypogravity; Data Transfer for Multiple Sensor Networks Over a Broad Temperature Range; Using Combustion Synthesis to Reinforce Berms and Other Regolith Structures; Visible-Infrared Hyperspectral Image Projector; Three-Axis Attitude Estimation With a High-Bandwidth Angular Rate Sensor Change_Detection.m; AGATE: Adversarial Game Analysis for Tactical Evaluation; Ionospheric Simulation System for Satellite Observations and Global Assimilative; Modeling Experiments (ISOGAME); An Extensible, User- Modifiable Framework for Planning Activities; Mission Operations Center (MOC) - Precipitation Processing System (PPS) Interface Software System (MPISS); Automated 3D Damaged Cavity Model Builder for Lower Surface Acreage Tile on Orbiter; Mixed Linear/Square-Root Encoded Single-Slope Ramp Provides Low-Noise ADC with High Linearity for Focal Plane Arrays; RUSHMAPS: Real-Time Uploadable Spherical Harmonic Moment Analysis for Particle Spectrometers; Powered Descent Guidance with General Thrust-Pointing Constraints; X-Ray Detection and Processing Models for Spacecraft Navigation and Timing; and Extreme Ionizing-Radiation-Resistant Bacteriu

Thermal Investigations Of Flip Chip Microelectronic Package With Non-Uniform Power Distribution [TK7874. G614 2004 f rb] [Microfiche 7607].

Arah aliran pempakejan sistem-sistem dan subsistem mikroelektronik adalah kearah pengurangan saiz dan peningkatan prestasi, di mana kedua-duanya menyumbang kepada peningkatan kadar penjanaan haba. The trend in packaging microelectronic systems and subsystems has been to reduce size and increase performance, both of which contribute to increase heat generation

피부 부착이 가능한 생체 통합 센서, 전하 트랩 메모리, 및 양자점 정보 디스플레이의 개발

학위논문 (박사)-- 서울대학교 대학원 : 화학생물공학부, 2017. 2. 김대형.최근 다양한 생리학적 데이터를 얻을 목적으로 인체에 붙일 수 있는 전자 장치를 개발하기 위해 많은 연구자들이 지속적인 노력을 기울여 왔습니다. 그러나 부드럽고 곡면으로 이루어 진 인체의 피부에 딱딱한 전자 장치를 장착하기 어려운 까닭에, 변형 가능한 전자 장치의 개발에 대한 필요성이 대두 되었습니다. 이와 관련하여, 유기 반도체 물질과 같은 본질적으로 유연한 물질뿐만 아니라 벌크 형태일 때에는 변형성이 부족하지만 그 두께 및 크기를 조절하여 변형이 용이하게 만들어진 나노 입자, 나노 와이어 및 나노 리본과 같은 초박형/초소형 물질이 인체 부착 형 전자 장치의 고성능 동작을 위한 주요 물질로 사용되기 시작하였습니다. 본 논문은 이러한 나노 물질을 다양한 목적으로 통합시킨, 피부와 유사한 기계적 성질을 가지는 피부 부착 형 전자 장치의 세 가지 예에 대한 연구 내용을 소개하고 있습니다. 첫 번째로, 초박막, 단결정 실리콘 나노 리본을 활용한 변형률, 압력 및 온도 센서 어레이와 더불어, 눅눅한 정도를 느낄 수 있는 습도 센서, 체온 모사를 위한 히터 및 신경 자극을 위한 신축성 다중 전극 어레이가 활용 된 스마트 인공 피부 보철 장치를 개발 하였습니다. 본 연구에서 개발된 피부 보철 장치는 사람의 피부와 비슷한 신축성을 가진 동시에, 사람의 피부가 느낄 수 있는 외부 자극을 느낄 수 있고, 사람의 체온을 모사 하는 등, 최대한 사람의 피부와 비슷한 특성 및 성능을 지니도록 고안되어 향후 로봇 팔, 의수 등에 적용 가능할 거라 기대합니다. 두 번째로, 나노 결정으로 이루어진 플로팅 게이트를 갖춘 피부 부착 형 비휘발성 메모리 어레이를 개발 하였습니다. 나노 결정 플로팅 게이트는 Langmuir-Blodgett 방법을 사용하여 넓은 영역에 걸쳐 균일하게 조립됩니다. 균일한 나노 결정 플로팅 게이트는 성능의 균일성을 향상시킴과 동시에, 메모리 윈도우 마진과 정보 저장 성능을 향상시킵니다. 또한, 초박형 실리콘 나노 멤브레인으로 제작 된 회로를 기반으로 한 증폭기와 늘일 수 있는 피부 부착 형 전극을 이용하여 심전도를 측정하고 심장 박동 수의 변화를 개발된 메모리에 저장하는 데모를 선보였으며, 이는 향후에 피부 부착 형 소자를 의료 어플리케이션에 적용할 수 있는 가능성을 열었다 할 수 있습니다. 세 번째로, 피부에 붙일 수 있는 초박형 양자점 발광 다이오드 디스플레이를 개발하였습니다. 먼저 낮은 작동 전압으로 높은 휘도를 얻기 위해 양자점을 구조적으로 최적화 시켰습니다. 이렇게 최적화된 양자점을 활용하여 양자점 발광 다이오드 어레이로 구성된 양자점 디스플레이를 디자인 하였으며 이의 활용성을 보이기 위하여 문자, 숫자, 기호 및 애니메이션으로 구성된 다양한 패턴이 피부에 부착된 양자점 디스플레이를 통해 보여 질 수 있음을 시연 하였습니다. 개발된 양자점 디스플레이의 사용 중 안정성을 입증하기 위해 구겨짐 및 반복되는 구부림과 같은 다양한 기계적 변형에도 성능에 영향이 없음을 확인 하였습니다. 또한, 입을 수 있는 전자 소자로의 활용성을 보이기 위하여 유연한 전자 장치를 디스플레이와 함께 집적하여 주변 온도 및 걸음 수를 측정하고 곧바로 피부에 부착된 디스플레이로 이를 확인할 수 있음을 시연 하였습니다. 본 논문에서 개발된 세 전자 장치는 미래의 피부 부착 형 전자 장치의 실현에 중요한 구성 요소입니다. 이번 연구 결과를 활용하여 변형 가능한 센서, 액추에이터, 데이터 저장 장치 및 디스플레이 분야에서 새로운 기회가 창출 되고, 완전히 통합된 피부 부착 형 전자 장치의 개발이 가속화되기를 기대합니다.1. Recent advances in deformable devices with integrated functional nanomaterials for wearable electronics 1 Preface 1 1.1 Introduction 3 1.2 Wearable sensors and actuators 6 1.3 Wearable memories 18 1.4 Wearable displays 23 1.5 Conclusion 26 References 27 2. Stretchable silicon nanoribbon based sensor array for skin prosthesis 39 2.1 Introduction 39 2.2 Experimental section 42 2.3 Results and discussion 49 2.4 Conclusion 94 References 95 3. Skin mountable multiplexed silicon nonvolatile memory for storing physiological information 101 3.1 Introduction 101 3.2 Experimental section 105 3.3 Results and discussion 109 3.4 Conclusion 145 References 147 4. Skin mountable quantum dot light emitting diode display for indicating measured data 154 4.1 Introduction 154 4.2 Experimental section 157 4.3 Results and discussion 161 4.4 Conclusion 190 References 191 국문 초록 (Abstract in Korean) 198Docto

A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator

Abstract-MEMS-based oscillators have recently become a topic of interest as integrated alternatives are sought for quartz-based frequency references. When seeking a programmable solution, a key component of such systems is a low power, low area fractional-N synthesizer, which also provides a convenient path for compensating changes in the MEMS resonant frequency with temperature and process. We present several techniques enabling efficient implementation of this synthesizer, including a switched-resistor loop filter topology that avoids a charge pump and boosts effective resistance to save area, a high gain phase detector that lowers the impact of loop filter noise, and a switched capacitor frequency detector that provides initial frequency acquisition. The entire synthesizer with LC VCO occupies less than 0.36 sq. mm in 0.18 m CMOS. Chip power consumption is 3.7 mA at 3.3 V supply (20 MHz output, no load). Index Terms-MEMS, fractional-N synthesizer, reference frequency, phase-locked loop (PLL), loop filter, high gain phase detector, switched resistor, switched capacitor, frequency acquisition, frequency detection, phase detection, oscillator, temperature stable

Integrated Circuits and Systems for Smart Sensory Applications

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight low-power or, in same cases even self-powered, smart devices with high-connectivity capabilities. CMOS integrated circuits technology is the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, power management strategies, low-range wireless communications, integration with sensing devices. In this Special Issue recent advances in application-specific integrated circuits (ASIC) and systems for smart sensory applications in the following five emerging topics: (I) dedicated short-range communications transceivers; (II) digital smart sensors, (III) implantable neural interfaces, (IV) Power Management Strategies in wireless sensor nodes and (V) neuromorphic hardware

Readout technologies for directional WIMP Dark Matter detection

The measurement of the direction of WIMP-induced nuclear recoils is a compelling but technologically challenging strategy to provide an unambiguous signature of the detection of Galactic dark matter. Most directional detectors aim to reconstruct the dark-matter-induced nuclear recoil tracks, either in gas or solid targets. The main challenge with directional detection is the need for high spatial resolution over large volumes, which puts strong requirements on the readout technologies. In this paper we review the various detector readout technologies used by directional detectors. In particular, we summarize the challenges, advantages and drawbacks of each approach, and discuss future prospects for these technologies

Readout technologies for directional WIMP Dark Matter detection

The measurement of the direction of WIMP-induced nuclear recoils is a compelling but technologically challenging strategy to provide an unambiguous signature of the detection of Galactic dark matter. Most directional detectors aim to reconstruct the dark-matter-induced nuclear recoil tracks, either in gas or solid targets. The main challenge with directional detection is the need for high spatial resolution over large volumes, which puts strong requirements on the readout technologies. In this paper we review the various detector readout technologies used by directional detectors. In particular, we summarize the challenges, advantages and drawbacks of each approach, and discuss future prospects for these technologies