A 5-MHz 11-bit delay-based self-oscillating ΣΔ modulator in 0.025 mm2

In this paper a self-oscillating Sigma Delta modulator is presented. By introducing this self-oscillation in the system, the loop filter operates at a speed significantly lower than dictated by the clock frequency. This allows for a simple and power efficient design of the opamps used in the loop filter. The self-oscillation is induced here by introducing a controlled delay in the feedback loop of the modulator. A second order CMOS prototype was constructed in a 0.18 um technology. A clock frequency of 850MHz generates a self-oscillation mode at 106.25 MHz. The modulator achieves a dynamic range (DR) of 66 dB for a signal bandwidth of 5 MHz. The power consumption is only 6mW and the chip area of the modulator core is 0.025mm^2

Architectures for maximum-sequence-length digital delta-sigma modulators

In this paper, we extend the idea developed in some of our earlier works of using output feedback to make the quantization step in a digital delta-sigma modulator (DDSM) appear prime. This maximizes the cycle lengths for constant inputs, spreading the quantization error over the maximum number of frequency terms, and consequently, minimizing the power per tone. We show how this concept can be applied to multibit higher order error-feedback modulators (EFMs). In addition, we show that the idea can be implemented in a class of single-quantizer DDSMs (SQ-DDSM) where STF (z) = z(-L) and NTF (z) = (1 - Z(-1))(L)

Adaptive noise cancellation for second-order delta-sigma A/D converters

Oversampled analog-to-digital (A/D) converter architectures have been receiving increased attention for high-precision A/D converters. These architectures offer the means of exchanging resolution in time for that in amplitude. Among these oversampled A/D converters, delta-sigma modulators are the most popular method used due to their simplicity in the analog circuitry. The analog integrators in delta-sigma modulators suffer from non-idealities such as capacitor mismatches and finite op-amp gain. In the dual quantizer A/D converters, the system relies on the perfect matching of the analog and digital transfer functions to cancel the quantization noise. However, the non-ideality of the analog parameters makes this matching hard to achieve. In this thesis, an off-line adaptive scheme is presented to estimate the non-ideal parameters of the analog section for the second-order delta-sigma modulator. These estimates are then used in the digital part to reduce the quantization noise. The least-mean- square (LMS) algorithm is used to adaptively estimate the analog parameters

Double-sampled cascaded sigma-delta modulator topologies for low oversampling ratios

This paper presents novel double-sampling cascaded sigma-delta modulator topologies for wideband applications. The proposed modulator structures employ finite impulse response (FIR) noise transfer function (NTF) to achieve the aggressive noise shaping with an additional zero at the half of the sampling frequency to alleviate the quantization noise folding. Cascading of the proposed modulator structures is very simple without any additional circuit requirements.Comisión Interministerial de Ciencia y Tecnología TIC2003-0235

Double-Sampling Single-Loop EA Modulator Topologies for Broad-band Applications

This paper presents novel double sampling high-order single loop sigma-delta modulator structures for wide-band applications. To alleviate the quantization noise folding into the inband frequency region, two previously reported techniques are used. The digital-to-analog converter's sampling paths are implemented with the single-capacitor approach and an additional zero is placed at the half of the sampling frequency of the modulator's noise transfer function (NTF). The detrimental effect of this additional zero on both the NTF and signal transfer function is also resolved through the proposed modulator architectures with a low additional circuit requirement

VCO-based sturdy MASH ADC architecture

A new multistage 1-1 ΔΣ analogue-to-digital converter (ADC) architecture implemented only with voltage-controlled oscillators (VCOs) is introduced. A sturdy multistage noise-shaping (SMASH) configuration is used to avoid the need of either calibration circuitry or noise-cancellation filters. The digital nature of the VCO's output simplifies the implementation of the interconnection paths between stages, making unnecessary neither the use of multibit digital-to-analogue converters nor analogue subtraction elements. The basic operation of the architecture is shown at system level and the sensitivity to VCO's frequency mismatch is analysed. The proposed architecture has been validated through behavioural simulations.This work was supported by the CICYT project TEC2014-56879-R, Spain

A rigorous approach to the robust design of continuous-time ΣΔ modulators

In this paper we present a framework for robust design of continuous-time Sigma Delta modulators. The approach allows to find a modulator which maintains its performance ( stability, guaranteed peak SNR, ...) over all the foreseen parasitic effects, provided it exists. For this purpose, we have introduced the S-figure as a criterion for the robustness of a continuous-time Sigma Delta modulator. This figure, inspired by the worst-case-distance methodology, indicates how close a design is to violating one of its performance requirements. Optimal robustness is obtained by optimizing this S-figure. The approach is illustrated through various design examples and is able to find modulators that are robust to excess loop delay, clock jitter and coefficient variations. As an application of the approach, we have quantified the effect of coefficient trimming. Even with poor trim resolution, good performance can be achieved provided beneficial initial system parameters are chosen. Another example illustrates the fact that also the out-of-band peaking behavior of the signal transfer function can be controlled with our design framework