This paper presents novel double-sampling cascaded sigma-delta modulator topologies for wideband applications. The proposed modulator structures employ finite impulse response (FIR) noise transfer function (NTF) to achieve the aggressive noise shaping with an additional zero at the half of the sampling frequency to alleviate the quantization noise folding. Cascading of the proposed modulator structures is very simple without any additional circuit requirements.Comisión Interministerial de Ciencia y Tecnología TIC2003-0235

Rodríguez Vázquez, Ángel Benito

Shoaei, Omid

Yavari, Mohammad

English

idUS. Depósito de Investigación Universidad de Sevilla

DOUBLE-SAMPLED CASCADED SIGMA-DELTAMODULATORTOPOLOGIES FOR LOW OVERSAMPLING RATIOStMohammad Yavari, Omid Shoaei, andAngel Rodriguez- Vazquez *IC Design Laboratory, ECE Department, University of Tehran, Tehran 14395-515, Iran* Instituto de Microelectronica de Sevilla (IMSE-CNM), 41012 Seville, SpainEmail: myavarigut.ac.irABSTRACT 02d CS2 CIThis paper presents novel double-sampling cascaded sigma-deltamodulator topologies for wideband applications. The proposed idmodulator structures employ finite impulse response (FIR) noise Vin Vcmo Vcmi 2transfer function (NTF) to achieve the aggressive noise shaping cm2d / _ Voutwith an additional zero at the half of the sampling frequency to 11alleviate the quantization noise folding. Cascading of the proposed ld 11modulator structures is very simple without any additional circuit CSIrequirements.1. INTRODUCTION Fig. 1: A single-ended double-sampling integrator.With the recent developments in both wired and wirelesscommunications, there is a need to design analog-to-digital where Cs = (Cs, + CS2)12, ACs = (Cs, - Cs2), and time n = 0 occursconverters (ADCs) at MHz speeds with high linearity at low when 2is high [3]. The first two terms of the right side in (1)voltage environments. Sigma-delta modulators and pipelined implements an ideal sample delaying integrator. But, the last termADCs are the two main candidates for high-resolution and high-speed applications. Pipelined converters need some type of in(1) istheproduct ofthe input signal and (-1)" which indicatescalibration or error correction techniques to achieve accuracies a modulation between the input signal and a sampled cosine at thebeyond 12-bits, resulting in increased complexity and power half of the sampling frequency (f,/2) through any mismatchdissipation. between the sampling capacitors. If the input is a low frequencySigma-delta ADCs are the main candidates for high resolution signal, this mismatch does not affect the inband frequencies.applications due to their inherent immunity to the circuit non- However, since the DAC output has a large high frequencyidealities [1]. In order to employ them in broadband applications, a quantization noise, this noise is folded into the inband frequencieslow oversampling ratio (OSR) should be employed. But, the if any mismatch exists between the DAC sampling capacitors.reduction of OSR decreases the accuracy of the modulator, Therefore, the SNDR is degraded. This is the main drawback ofdrastically. So, novel modulator structures are needed to alleviate double sampling modulators.the reduction of resolution in low OSR applications. Several techniques have been proposed to alleviate theA useful approach in switched-capacitor realizations of the quantization noise folding in doubled-sampled modulators such asmodulators is to employ the double-sampling technique [2]. In this employing the fully floating method in the feedback DAC pathsmethod, the circuit operates during both phases of the clock. and/or placing a zero at the half of the sampling frequency (f,/2) ofHence, the effective sampling frequency of the system is twice that the NTF, etc [3-5]. However, both techniques affect theof the clock frequency. This results in doubling the OSR or the modulator's NTF and signal transfer function (STF) and hence theavailable time for settling of the integrators if OSR is fixed. Figure modulator's noise shaping ability. So, their effects should be1 shows a single-ended double-sampling integrator. In this circuit, considered in the design of the modulator's NTF to achieve antwo distinct capacitors are used to sample the input signal. The aggressive noise shaping. In this paper, efficient high order doublecapacitor Cs, is used to sample the input signal at the phase 01 sampling cascaded sigma-delta modulators are proposed.while at this interval the stored charge on Cs2 is transferred into the 2. PROPOSED MODULATOR TOPOLOGIESintegrating capacitor, CI. At the next phase, 02, CS2 samples theinput signal and Cs, transfers its stored charge into CI. Hence, in The general structure of a sigma-delta modulator is shown in Fig. 2both phases of the clock, the sampling and integrating is performed where H(z) is the loop transfer function and its NTF is given byresulting in doubling the effective sampling rate of the system. 1The signal transfer function of the double sampling integrator NTF(z) = (2)with an ideal opamp can be written as 1+ H(z)VOW [n] = VOW [n-i] + CS VJ [n-] + (-1) ACs Vin [n-l] (1) The NTF of the proposed second-order double-sampling sigma-CI 2CI delta modulator is considered as an FIR filter:ANTllF(Z) = (1A -1 \2 ( 1 + Z-1 \SO, H(Z) iS obtained as follows:t This work has been supported in part by the Spanish project TIC2003-02355 (RAICONIF).0-7803-9390-2/06/$20.00 ©)2006 IEEE 597 ISCAS 2006-1 ( -1 The double-sampling resonator with a unit delay can beH[(z)= 1_ 1-zn I (4) implemented using only one opamp as proposed in [5]. So, onlytwo opamps like the conventional second-order modulator areHence, the structure of the proposed second-order modulator will needed to realize the circuit of the proposed second-orderbe as shown in Fig. 3. This structure is composed of an integrator, modulator. The paths terminating to the input of the quantizer cana resonator, and a quantizer. A resonator is used instead of an be realized using a passive switched-capacitor circuit.integrator to realize a zero ofNTF atfs/2. To cascade the proposed second order modulator, the output ofIn this structure, the signal transfer function (STF) is unity. the resonator can be used directly since it is only a function of theUnity gain STF in a sigma-delta ADC has many advantages such quantization noise and is as follows:as the followings. First, the effects of the circuit non-idealities such U(z) = - z2 EQ(z) (5)as the limited opamp DC gain and nonlinearities are reduced sinceonlythequatizaionnoie isproessd bytheintgratrs 6]. where EQ(z) is the quantization error and is assumed as an additiveSeond,the dyntami rnge isincresed be the onlelemets6 white noise. The structure of the proposed cascade 2-2 is shown inSecond, the dynamic range iS creased because the only elements Fig. 4. This architecture employs the roposed second order as thethat have to accommodate the full input signal swing are the Fig. 4. Toachieve theyu p proposed muchrduceswitches and the quantizer and the output swing of the opamps stnstage to a he doublets much r educeddoeno lii th iptsgaamlud .Thr,teinertr sensitivity to the sampling paths mismatch. In the second stageneedsmlnoutpt sweinpuigs another second order modulator with unity gain STF and FIR NTFis used. The NTF zeros of the second stage are placed into theinband frequencies to achieve the aggressive noise shaping in lowX(z) i b-bit Y(z) OSRs.H°z) ADClIt can readily be shown that the sampling paths mismatch of thefirst integrator is shaped by the first order. The sampling pathsb-bit mismatch of the resonator, third and fourth integrators are shapedsecond, third and fourth orders, respectively. On the other hand,Fig. 2: General structure of a sigma-delta modulator. due to the employing a multibit quantizer the out-of-bandquantization noise will be lower than the case of using a single bitquantizer. Therefore, the multibit quantization also reduces theX(z) iIU) tY(Z)__ __ n_ nitX(z) - I __ U(z) n-bitY(z)C sensitivity of modulator to the sampling paths mismatch.z-1.-It is worth mentioning that the order of the proposed cascadedmodulators can simply be extended to high orders efficiently. Forn-bit example, in cascade 2-2-2 the proposed second-order modulator isDAC used in the first stage. The second and third-stages can employ theconventional second-order structure with NTF's zeros optimized atFig. 3: The proposed second-order double-sampling modulator. teibnfrqncsfoagesveosehpn.* the inband frequencies for aggressive noise shaping.59(ZI aX (z)l E l~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~......................x> :~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.....................( aA l~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~......................9593. SYSTEM-LEVEL SIMULATION RESULTS SNDR of the modulator considerably as it is seen in Fig. 8.However, it should be noted that since the sampling capacitors ofTo show the usefulness of the proposed cascade 2-2 double- the first integrator are large due to the circuit noise considerations,sampling modulator topology, its system level architecture taken a paths mismatch of about 0.11% is readily realizable.into account the circuit non-idealities was simulated withMATLAB. In these simulations, the OSR and quantizer resolutionsof the first and second stages were selected as 8, 5-bit and 3-bit, -50 -dBFS- -s -- -Inrespectively. The coefficient a is needed to place two zeros of Inband * iNTF at the inband frequencies. The design method proposed by --1 00 - - - - I I rSchreier [7] is used to obtain the value of a in order to place the / Iinband zeros at the optimal points. The other coefficients are -150 - Iobtained such that the NTF of both stages become the high passFIR filters. Then, signal scaling is performed to get the signal -200 '''1 -2 I -iswing about full scale range at the quantizers' input. This results in 10 Normalized frequency f = 1)the second stagequan ization noise to bNormalizedsfrequencytimes1the second stage quantization noise to be decreased by 16 times. Figure 6: Output spectrum including the circuit non-idealities.So, the modulator coefficients are as follows:al=bl=2, a2=2, g1= 1 g2=I/2, g3=I/4, a3=2,b3=I/2, 8000 - FirstIntg.a4= 1, g4= 4, g5= 2, g6= 16/9, a = 1/9,, = 1/16 (6) - -1.4-dBFSsininput hirIntg.I~~~~~~Fourth fitg.Figure 5 shows the ideal output spectrum of the proposed °4000-cascade 2-2 modulator. The resultant maximum SNDR is about 97-dB. With including the circuit non-idealities the maximum SNDR 2000-_---____-- __0is about 94-dB as shown in Fig. 6. These non-idealities include theDC gain of the first integrator and resonator of 70 dB, the DC gain -0.1 0.2-0.2 -0.1 ~0 0.102of third and fourth integrators of 50 dB, 0.2% mismatch between Normalized output signal swings (Vref = 1)the coefficients a1, b1 and a2 , 1% mismatch between the other Figure 7: Building blocks output swings.coefficients, 0.1% mismatch between sampling paths of the firstintegrator, and 0.5% mismatch between sampling paths of the 98other blocks. Simulation results indicate that the signal swings atthe output of the integrators and resonator are much less than the- B nreference voltage level as it is shown in Fig. 7 due to the unity-gain 2 9LSSTF and also feedforward paths. This results in demanding low a First lntg.-_swing analog building blocks making the circuit design more z - 2Resonator_~2- Third Intg. I I Qrelaxed especially in low voltage applications. + Fourth lntg.90L____ ________0 0.1 0.2 0.3 0.4 0.5Samplig paths mismatch (%/6)-1.4 dBFS sin inpu i-50 - 7_ _ _ _ _ - o 1-7-7nFl-T - - X - F - Fig. 8: SNDR degradation versus the sampling paths mismatch.m * Inband * lin-100 -- I---- I--- | | l4. CIRCUIT IMPLEMENTATION-150 iII IXI Figure 9 shows the switched-capacitor realization of the proposedI7I I I I I I11IllII I I I 1second-order modulator. As it is seen the first integrator can be-200 I I II I I I I L implemented using the conventional double-sampling integrators.io-3 10o-2 10o The double-sampling resonator is realized by employing twoNormalized frequency (fs = 1) integrating capacitors in a conventional double-samplingFigure 5: Simulated ideal output spectrum. integrator. Each of these capacitors is used only in one clockphase. The addition of the signals preceding the quantizer can beAs mentioned before, the main concern of double-sampled ..modulators is the quantization noise folding due to the sampling implemented by a passive switched-capacitor circuit as shown inpaths mismatch. Figure 8 shows the SNDR degradation versus the Fig. 9. In this circuit, the comparators' reference voltages are alsomismatch of the sampling paths. As it is seen the SNDR subtracted from the input signal of the comparators to make thedegradation of the proposed cascade 2-2 is negligible even with a desired decision.0.10% mismatch between the sampling paths of the first integrator.The paths mismatch of the remaining blocks does not affect the599l./ ....lllli.................... ... ..... ...............................................................................................................................................................................2d CS202C102Op.OldVcmoVin+ &-j--Vdqtd+Q- Vdnli 0- I01I) / 02d Oi'__1IVo2pOid 02 1 P Old q2CS2tLLL=L.Vcnio C._joii Cii 0 ln .ld+ 02z +H 11._Vin- o-4-- Vdg&o-- Vdnli 0- 0- Vcmi 0- \ \oi Cil / Old / 0202L_ 11:__ TKI 11HHHHX.Oidoi': ........(.S'2 O''......................HHHI.Integrator Resonator..vcmoo.....O.1,12.r.....4j\027,..Fig. 9: Switched-capacitor implementatio:..*---O.:01, Old tw,.:.-- .-),:td02,02d . . ::O, 1. t, ._ J----.O___O. ).:4TFig. 10: Clock waveforms.Figure 10 shows the clock waveforms. Two non-overlappingclock phases and their delayed versions are used for samplingand integrating. Another clock phase is needed in thecomparators. As shown in Fig. 10, 0, is used to regenerate thelatches of the comparators. When 0, is low, the latches are inregeneration. As 0, goes to high, the latches are in the resetmode. This clock phase can be realized by a simple gating of themain non-overlapping clocks.It is worth mentioning that since the charge transferring of theDAC sampling capacitors is performed without any delay, theunit feedback delay of the first integrator is devoted to thequantizer and DAC linearizatioerrors resulted from the DAC unit elements mismatch, DAClinearization techniques such as DWA can also be used [1].April5. CONCLUSIONSIn this paper, novel double-sampled second-order and cascadedllio-mq ili-ltq mnt1ii1qtnr tnnn1no,ii-Q fnr hrnqc1hqnc1 qnnflrqflnnQ

Double-sampled cascaded sigma-delta modulator topologies for low oversampling ratios

https://idus.us.es/bitstream/11441/92033/1/DOUBLE-SAMPLED%20CASCADED%20SIGMA-DELTA%20MODULATOR.pdf

Double-sampled cascaded sigma-delta modulator topologies for low oversampling ratios

Abstract

Similar works

Full text

Available Versions

idUS. Depósito de Investigación Universidad de Sevilla