In this paper a self-oscillating Sigma Delta modulator is presented. By introducing this self-oscillation in the system, the loop filter operates at a speed significantly lower than dictated by the clock frequency. This allows for a simple and power efficient design of the opamps used in the loop filter. The self-oscillation is induced here by introducing a controlled delay in the feedback loop of the modulator. A second order CMOS prototype was constructed in a 0.18 um technology. A clock frequency of 850MHz generates a self-oscillation mode at 106.25 MHz. The modulator achieves a dynamic range (DR) of 66 dB for a signal bandwidth of 5 MHz. The power consumption is only 6mW and the chip area of the modulator core is 0.025mm^2

De Vuyst, Bart

Rombouts, Pieter

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5-MHz 11-bit delay-based self-oscillating &#x03A3;&#x0394; modulator in 0.025mm<sup>2</sup>

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1A 5-MHz 11-bit Delay-BasedSelf-Oscillating Σ∆ Modulator in 0.025mm2Bart De Vuyst, Pieter RomboutsThis document is an author’s draft version submitted for publication the IEEE CICC conference 2010,The actual version was published as:Bart De Vuyst, Pieter Rombouts, “A 5-MHz 11-bit Delay-Based Self-Oscillating Σ∆ Modulator in 0.025mm2,” IEEE CustomIntegrated Circuits Conference (CICC), 19-22 Sept. 2010, San Jose, USA1A 5-MHz 11-bit Delay-BasedSelf-Oscillating Σ∆ Modulator in 0.025 mm2Bart De Vuyst, Pieter RomboutsGhent University (UGent), Dept. ELIS, Sint-Pietersnieuwstraat 41, 9000 Ghent, BelgiumEmail: bart.devuyst,rombouts@elis.UGent.beAbstract—In this paper a self-oscillating Σ∆ modulator ispresented. By introducing this self-oscillation in the system, theloop filter operates at a speed significantly lower than dictatedby the clock frequency. This allows for a simple and powerefficient design of the opamps used in the loop filter. The self-oscillation is induced here by introducing a controlled delay in thefeedback loop of the modulator. A second order CMOS prototypewas constructed in a 0.18µm technology. A clock frequency of850 MHz generates a self-oscillation mode at 106.25 MHz. Themodulator achieves a dynamic range (DR) of 66 dB for a signalbandwidth of 5 MHz. The power consumption is only 6 mW andthe chip area of the modulator core is 0.025 mm2.I. INTRODUCTIONΣ∆ modulators are known to realize high resolution analog-to-digital (A/D) converters. To increase the bandwidth andreduce the power consumption of these converters, continuous-time (CT) Σ∆ modulators have proven to be a good solution.In contrast to discrete-time (DT) Σ∆ modulators, here theunity gain-bandwidths (GBWs) of the opamps used in the loopfilter only have to exceed the sample frequency fs by a factor2 or less. This way higher sample frequencies can be used andthe bandwidth can be extended into the wide MHz range.To achieve these high bandwidths, usually a low oversam-pling ratio (OSR) is combined with a multibit quantizer [1],[2]. However, as the number of comparators rises exponen-tially with the number of bits in a flash quantizer, this increasesboth chip area and circuit complexity [3]. Furthermore, also amultibit digital-to-analog converter (DAC) has to be included.As this DAC is situated in the feedback path its linearitymust at least be equal to the modulator’s resolution. Thereforetypically dynamic element matching (DEM) techniques arerequired. CT Σ∆ modulators are also sensitive to clock jitterwhen using non-return-to-zero (NRZ) or return-to-zero (RZ)pulses in the feedback DAC. This gives rise to extra jitter noisein the signal band [4].Recently, time-encoding has shown to be a promising tech-nique to avoid multibit quantization [5], [6]. The input isthereby encoded into the output signal through pulsewidthmodulation. For this purpose we consider a CT Σ∆ modulatorwhich operates in a self-oscillating mode in this paper. Theself-oscillating frequency is an integer fraction of the samplefrequency fs. It is controlled by introducing a digital delayin the feedback path. This way the system globally worksat a much lower speed than fs and the opamp GBWs aresignificantly relaxed. Jitter sensitivity is also heavily reducedΣ Dout(z)fsVin(s) H(s)−DAC(1b) z−dAsin(ωct) + CFig. 1. Block diagram of a delay-based self-oscillating Σ∆ modulator.as the feedback DAC signal toggles at a lower rate. Also, onlya 1-bit quantizer (comparator) and feedback DAC are required.II. DELAY-BASED SELF-OSCILLATINGCT Σ∆ MODULATORFig. 1 shows the basic architecture for the delay-based self-oscillating Σ∆ modulator. It consists of a loop filter H(s),a comparator clocked at fs, a single-bit feedback DAC anda digital delay of d clock cycles. In [7] a similar system ispresented, except for the fact that a hysteresis based compara-tor is used to induce self-oscillation in the Σ∆ loop. However,the rest of the analysis made there remains valid for the delay-based modulator.The system shown in fig. 1 is non-linear due to the presenceof the comparator and therefore hard to analyze. In [8] thedescribing-function theory is proposed as a way to linearizethese systems. The system is described by considering thebehaviour for a superposition of different kinds of signalsat the comparator input. For each type of these signals thecomparator is linearized. In this case the comparator inputcan contain two types of signals: a first contribution from theself-oscillating output and a second contribution originatingfrom the input signal Vin(s).A. System Behaviour for the Self-Oscillation ModeWe assume a zero input when investigating the systembehaviour for the self-oscillation mode. The output signal isthen a square wave signal of frequency fc. This signal is low-pass filtered through the loop filter H(s). Therefore only thefirst order harmonic is accounted for in fig. 1. A sine wave withamplitude A and frequency ωc = 2pifc appears at the input ofthe quantizer. In [8] it is now stated that the quantizer can bereplaced by a linear gain which depends on the amplitude A2Σ Dout(z)fsH(s)−DAC(1b) e−sdTs4piAFig. 2. Behaviour of the system for the self-oscillation.of this sine wave (see fig. 2). The equivalent comparator gainequals:GC,SO =4piA(1)As we now have a fully linear loop, the digital delay can bereplaced by analog phase shift e−sdTs . A neccessary conditionfor the sine wave to reappear at the input of the comparatoris now that the combination of the loop filter, the delay, theDAC pulse and the sampler give rise to a 180 ◦phase shiftfor the frequency fc. Due to the presence of the sampler theoscillation frequency can only be an integer fraction of thesample frequency [7]. This condition results in a solution forA, the amplitude of the self-oscillating signal, which can beused to determine the equivalent comparator gain.B. System Response to the Input SignalA linearization of the comparator can also be performedwhen considering the contribution of the input signal to thecomparator input. The assumption made here is that the inputsignal is very low-frequent compared to the self-oscillation,so that the contribution of the input signal in fig. 1 can beconsidered to be a DC value C. The equivalent comparatorgain now equals:GC,in =2piA(2)This is only half the value as it was for the self-oscillationmode and is still dependent on the amplitude A of the self-oscillating signal. In fig. 3 the situation is depicted. Theinput now modulates the self-oscillation in pulsewidth. As thesampler is still present, the pulsewidth can only be modulatedin discrete steps of the sampling period Ts. This can beseen as a quantization error similar to a conventional multibitquantizer. The presence of the low-pass loop filter makes surethis quantization error is suppressed in the signal band.Σ Dout(z)fsH(s)−DAC(1b)2piAe−sdTsFig. 3. Behaviour of the system for the low-frequency input signal.Σ Vout(z)fsVin(s)DAC(1b)Σ−c2sc1sz−1−z−12DACFIR(4t)g−Fig. 4. Block diagram of the self-oscillating Σ∆ modulator.C. Comparison to a Conventional Σ∆ ModulatorAn interesting point of view is the comparison of this systemto a conventional Σ∆ modulator. As already stated whenapplying zero input the system generates a self-oscillatingsignal of frequency fc. This can be seen as a limit cyclegenerated by a conventional Σ∆ modulator operating at aclock frequency of 2fc. An equivalent OSR can be determinedfor the signal bandwidth fb:OSR =fcfb(3)The pulsewidth modulation of the self-oscillating output bythe input signal can be seen as an equivalent multibit quantizerwith a number of levels equal to fsfc .III. SYSTEM LEVEL DESIGNIn fig. 4 the block diagram of the implemented system isshown. It consists of a second order loop filter with localfeedback for zero spreading. The self-oscillation frequency,which is at a relative high frequency compared to the integratorcoefficients, is mainly determined by the first-order inner loop.One unit delay is introduced to supply enough phase shiftfor oscillation at fs8 . This way, when applying zero input,the output signal only toggles once every 4 clock cycles. Theouter loop has a half clock cycle delay to relax the settling ofthe comparator. Also, a uniform 4-tap finite-impulse-response(FIR) DAC is included here:HFIRDAC(z) =14(1 + z−1 + z−2 + z−3)(4)Jitter sensitivity is further reduced this way. Finally, a feed-inpath from the input is also present to reduce to output swingof the first integrator.As such the system behaves similar to a conventional Σ∆modulator with clock frequency fs4 and a 3-bit quantizer. Thesignal bandwidth fb is fixed at fs170 . The equivalent OSRbecomes 21.25. The resulting system parameters are shownin table I.A simulated output spectrum is shown in fig. 5. A -4.3 dBinput relative to full scale (dBFS) is applied. The inputfrequency equals fb5 . The edge of the signal band and the3TABLE ISELF-OSCILLATING Σ∆ MODULATOR SYSTEM PARAMETERSParameter System level value Circuit level valuec1 0.05fs 42.5 MHzc2 0.05fs 42.5 MHzg 0.0046 0.0046fs 850 MHzfc fs/8 106.25 MHzfb fs/170 5 MHzOSR 21.25 21.25nominal oscillation frequency are indicated by the two verticallines. Clearly the output contains a lot of content around theoscillation frequency. Due to the pulsewidth modulation ofthe oscillation mode by the input, spectral broadening appearsaround fs8 . The resulting signal-to-noise ratio (SNR) equals64.5 dB. Because of the nonlinear nature of the system, a thirdorder harmonic is also present at -78 dB relative to the carrier(dBc).IV. CIRCUIT LEVEL DESIGNA CMOS prototype is designed in a 0.18µm technology.A clock frequency of 850 MHz is chosen, based on theminimum required settling time for the comparator. This waythe oscillation frequency fc equals 106.25 MHz and the signalbandwidth fb equals 5 MHz. All the actual values of thesignificant system parameters on the circuit level can also befound in table I.The system is implemented using fully differential circuits.The integrators are formed with active-RC feedback opamps.Due to the resistive loads a two-stage Miller compensatedopamp topology is used for both integrators. Fig. 6 shows theschematic of this opamp. A series resistor Rz is included withthe compensation capacitor CC to cancel the effect of a right-halfplane zero. The common-mode feedback (CMFB) controlsignal is applied at the NMOS transistors in the first stage.The common-mode voltage is sensed with a resistive voltage10 -4 10 -3 10 -2 10 -1-140-120-100-80-60-40-20010 -5f/fsamplitude(dBFS)SNR=64.5 dBHD3=-78dBcFig. 5. Simulated output spectrum for a -4.3 dBFS input signal at fb/5.CMFBRz CCVb2PVin+Vb1PVout+Vin−CMFBRzCCVout−Vb2PFig. 6. Miller compensated two-stage operational amplifier used for theintegrators.divider at the outputs (not shown in fig. 6) and compared toa reference value using an auxiliary amplifier.The feedback signals are implemented using resistive DACs.They are digitally controlled by standard cell flipflops. Thecomparator is implemented as a pre-amplifier followed by alatch. The pre-amplifier is a simple PMOS differential pairloaded with ordinary active load NMOS transistors, verysimilar to what was used in [9].V. EXPERIMENTAL RESULTSFig. 7 shows a microphotograph of the prototype chipfabricated in a single-poly six-metal layer 0.18µm digitalCMOS process. The modulator core area is only 0.025 mm2.The power consumption is 6 mW from a 1.8 V supply voltagefor fs equal to 850 MHz. 85 % of the power is consumed inthe analog parts of the chip and only 15 % in the digital controlfor the feedback DACs.A measured output spectrum is shown in fig. 8. The inputconditions are equal to the ones from fig. 5 (-4.3 dBFS inputtone at 1 MHz). A full scale input corresponds to a sine wavewith an amplitude of 1.8 V. High correlation between themeasured spectrum and the simulated spectrum can be ob-served. The resulting SNR equals 61.1 dB now. Also second-order and third-order distortion appear at -57 dBc and -70 dBcrespectively. Especially the second-order distortion is worryingas it limits the signal-to-noise and distortion ratio (SNDR)of the modulator. Imbalance in the differential behaviour ofthe system, more precisely rise and fall time issues in thestandard cell flipflops seemed to be the cause of this distortion.However, this is a non fundamental problem which could befixed in future designs.In fig. 9 the SNR, SNDR and the SNDR without theinclusion of the second-order distortion is shown in functionFig. 7. Microphotograph of the 0.18µm CMOS prototype.4f (Hz)amplitude(dBFS)103 104 105 106 107 108-140-120-100-80-60-40-200SNR=61.1 dBHD2=-57dBcHD3=-70dBcFig. 8. Measured output spectrum for a 1 MHz, -4.3 dBFS input signal.of the input amplitude. The peak SNR of 61.1 dB is foundfor the -4.3 dBFS input. Even for a full scale input the SNRis still 50,2 dB. However, distortion becomes quite large then,which lowers the SNDR to 41.8 dB. As one can see second-order distortion is clearly dominant as the SNDR alreadystarts dropping at much lower input signal levels comparedto the situation where second-order distortion was neglected.The dynamic range of the modulator equals 66 dB whichcorresponds to an 11-bit resolution. Based on the powerconsumption we can estimate a figure of merit (FOM) forour prototype:FOM =P2fb2B(5)This FOM equals 360 fJ/conversion step for our design.Input amplitude (dBFS)SNR,SNDR,SNDRw/oHD2(dB)-70 -60 -50 -40 -30 -20 -10 0010203040506070Fig. 9. SNR (solid), SNDR (dashed-dotted) and the SNDR without secondorder distortion (dashed) in function of the input amplitude.VI. CONCLUSIONIn this paper a second order self-oscillating Σ∆ modulatorfabricated in a 0.18µm CMOS process was presented. Theintroduction of a controlled delay in the feedback loop causesthe system to oscillate at 106.25 MHz for a clock frequencyof 850 MHz. The modulator achieves a dynamic range (DR)of 66 dB for a signal bandwidth of 5 MHz. This correspondsto an 11-bit resolution. Due to the simplicity of the circuit,the modulator core area is only 0.025 mm2. The power con-sumption of the modulator is 6 mW resulting in a FOM of360 fJ/conversion step.VII. ACKNOWLEDGEMENTThis work was supported by the Fund for Scientific Re-search (F.W.O.-Vlaanderen, Belgium).REFERENCES[1] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and E. Ro-mani, “A 20-mW 640-MHz CMOS Continuous-Time Σ∆ ADC With20-MHz Signal Bandwith, 80-dB Dynamic Range and 12-bit ENOB,”IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2641–2649, 2006.[2] Pato´n, S. and Di Giandomenico, A. and Herna´ndez, L. and Wiesbauer,A. and Po¨tscher, T., “A 70-mW 300-MHz CMOS Continuous-Time Σ∆ADC With 15-MHz Bandwidth and 11 Bits of Resolution,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1056–1062, 2004.[3] J. De Maeyer, P. Rombouts, and L. Weyten, “Efficient Multibit Quantiza-tion in Continuous-Time Σ∆ Modulators,” IEEE Trans. Circuits Syst.-I,vol. 54, no. 4, pp. 757–767, Apr. 2007.[4] K. Reddy and S. Pavan, “Fundamental limitations of continuous-timedelta-sigma modulators due to clock jitter,” IEEE Trans. Circuits Syst.-I,vol. 54, no. 10, pp. 2184–2193, 2007.[5] E. Prefasi, L. Hernandez, S. Paton, A. Wiesbauer, R. Gaggl, and E. Pun,“A 0.1 mm2, Wide Bandwith Continuous-Time Σ∆ ADC Based ona Time Encoding Quantizer in 0.13-µm CMOS,” IEEE J. Solid-StateCircuits, vol. 44, no. 10, pp. 2745–2754, 2009.[6] F. Colodro and A. Torralba, “New continuous-time multibit sigma-deltamodulators with low sensitivity to clock jitter,” IEEE Trans. Circuits Syst.-I, vol. 56, no. 1, pp. 74–83, 2009.[7] S. Ouzounov, A. Hegt, and A. van Roermund, “Sigma-delta modulatorsoperating at a limit cycle,” IEEE Trans. Circuits Syst.-II, vol. 53, no. 5,pp. 399–403, 2006.[8] A. Gelb and W. E. Vander Velde, Multiple-Input Describing Functionsand Nonlinear System Design. McGraw-Hill, 1968.[9] P. Rombouts, W. De Wilde, and L. Weyten, “A 13.5-b 1.2-v micropowerextended counting a/d converter,” IEEE J. Solid-State Circuits, vol. 36,no. 2, pp. 176–183, 2001.

A 5-MHz 11-bit delay-based self-oscillating ΣΔ modulator in 0.025 mm2

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A 5-MHz 11-bit delay-based self-oscillating ΣΔ modulator in 0.025 mm2

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