High-resolution width-modulated pulse rebalance electronics for strapdown gyroscopes and accelerometers

Three different rebalance electronic loops were designed, implemented, and evaluated. The loops were width-modulated binary types using a 614.4 kHz keying signal; they were developed to accommodate the following three inertial sensors with the indicated resolution values: (1) Kearfott 2412 accelerometer - resolution = 260 micro-g/data pulse, (2) Honeywell GG334 gyroscope - resolution = 3.9 milli-arc-sec/data pulse, (3) Kearfott 2401-009 accelerometer - resolution = 144 milli-g/data pulse. Design theory, details of the design implementation, and experimental results for each loop are presented

Neural network algorithm-based fall detection modelling

Fall is a major threat among elderly people which may lead to injuries or even death. High recognition of developed fall detection model is very significance for the elderly to detect the falls. Related algorithm for the fall detection has been discussed in depth by researcher from the previous research. However, the improvement of model accuracy is still needed. This article presents results of modelling for fall detection system by using nonlinear autoregression neural network NARnet algorithm. The algorithm is trained by network training function; LM, SCG and RP by collocation with threshold-based setting value. Two participants involved in obtaining the acceleration and angular velocity. The type of input source is divided into 4 different types for training. The selection of the model was based on the comparison of optimization epochs, magnitude of validate error or mean square error (MSE), magnitude of correlation performance, the convergence graph in term of MSE performance, accuracy of regression and non-zero value of autocorrelation graph. The simulated result shows that the training model of Type 2 is the best model with a training result of 6.1551mse, 40 epochs, time 0.06s, and 0.92742 accuracy. The result indicates that LM function produce the better solution when compared to another optimization function. In fact, the model accuracy demonstrated that the proposed method was reliable and efficient

Design and Analysis of High Gain Low Power CMOS Comparator

The comparator is the most significant component of the analog-to-digital converter, voltage regulator, switching circuits, communication blocks etc. Depending on the various design schemes, comparator performance varied upon target applications. At present, low power, high gain, area efficient and high-speed comparator designed methods are necessary for complementary metal oxide semiconductor (CMOS) industry. In this research, a low power and high gain CMOS comparator are presented which utilized two-stage differential input stages with replication of DC current source to achieve higher gain, higher phase margin, higher bandwidth, and lower power consumption. The simulated results showed that, by using a minimum power supply of 1.2 V, the comparator could generate higher gain 77.45 dB with a phase margin of 60.08°. Moreover, the modified design consumed only 2.84 µW of power with a gain bandwidth of 30.975 MHz. In addition, the chip layout area of the modified comparator is found only 0.0033 mm2

A wideband linear tunable CDTA and its application in field programmable analogue array

This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio

Design and Simulation of Two Stage Wideband CMOS Amplifier in 90 NM Technology

Design and simulation of 7 GHz CMOS wideband amplifier(CMOSWA) using a modified cascode circuit realized in  90-nm CMOS technology is presented here. The proposed system consists of two stages, namely a modified folded cascode and an inductively degenerated common source amplifier. The circuit is experimented with and without a feedback network. This work discusses the performance variation as a function of reactive components, and the initial stage results in 22 dB gain,2.6 GHz bandwidth, and 40GHz unity gain-bandwidth. The circuit without the feedback network exhibits 30.7dB gain,4.8GHz bandwidth(BW), and 10GHz unity-gain bandwidth(UGB). The reactive feedback network's inclusion helped to achieve 38.7 dB gain, 6.95GHz BW, 30GHz UGB, and 55o phase margin. The circuit consumes 1.4mW power from a 1.8V power supply. Simulation results of the proposed circuit are comparable and better than the reported wideband designs in the literature. Realization of our proposed circuit would add value to the area of wideband amplifier design

Design of a High Performance Silicon Carbide CMOS Operational Amplifier

This thesis presents the design, simulation, layout and test results of a silicon carbide (SiC) CMOS two-stage operational amplifier (op amp) with NMOS input stage. The circuit has been designed to provide a stable open-loop voltage gain (60 dB), unity-gain bandwidth (around 5 MHz) and maintain a high CMRR and PSRR within a useful input common mode range over process corners and a wide temperature range (25 °C - 300 °C). Between the two stages a Miller compensation topology is placed to improve the phase margin (around 45°). Due to the comparatively high threshold voltage values of transistors in SiC, the power supply is maintained at 15 V. There is a maximum of 21% variation in DC gain from 25 °C to 275 °C and the unity-gain bandwidth and slew rate improves with higher temperature. The major application area of this op amp is in high temperature environments where silicon (Si) integrated circuits (IC) fail to perform. In addition, the design of a second version of the operational amplifier is covered, which aims to provide more functionality and improved performance

Implicit feed-forward compensated op-amp with split pairs

Disclosed are systems implementing an implicit Feed-Forward Compensated (FFC) op-amp, where the main FFC port is realized by the P-side of the CMOS input structure of the 2nd and 3rd stages of the op-amp, while the main signal path is through the N-side. According to some embodiments, to balance the relative strengths of the main path and feed-forward paths, the 2nd-stage NMOS input pair is split into two pairs, one is used to route the main path while the other is used for auxiliary FFC. The disclosed implicit FCC op-amp is unconditionally stable with adequate phase lead. According to some embodiments, the disclosed op-amp, which may be a wide-band op-amp, can be used in highly linear applications operative at intermediate frequency (IF), such as signal buffers for high-performance data converters or radio-frequency (RF) modulators and demodulators, continuous-time (CT) filters or sigma-delta data converters.Board of Regents, University of Texas Syste

A Silicon Carbide Power Management Solution for High Temperature Applications

The increasing demand for discrete power devices capable of operating in high temperature and high voltage applications has spurred on the research of semiconductor materials with the potential of breaking through the limitations of traditional silicon. Gallium nitride (GaN) and silicon carbide (SiC), both of which are wide bandgap materials, have garnered the attention of researchers and gradually gained market share. Although these wide bandgap power devices enable more ambitious commercial applications compared to their silicon-based counterparts, reaching their potential is contingent upon developing integrated circuits (ICs) capable of operating in similar environments. The foundation of any electrical system is the ability to efficiently condition and supply power. The work presented in this thesis explores integrated SiC power management solutions in the form of linear regulators and switched capacitor converters. While switched-mode converters provide high efficiency, the requirement of an inductor hinders the development of a compact, integrated solution that can endure harsh operating environments. Although the primary research motivation for wide bandgap ICs has been to provide control and protection circuitry for power devices, the circuitry designed in this work can be incorporated in stand-alone applications as well. Battery or generator powered data acquisition systems targeted towards monitoring industrial machinery is one potential usage scenario

Low Power Operational Amplifier In 0.13um Technology

Low power is one of the most indispensable criteria in several of application. In this paper a low power operational amplifier consists of two stages and operates at 1.8V power. It is designed to meet a set of provided specification such as high gain and low power consumption. Designers are able to work at low input bias current and also at low voltage due to the unique behavior of the MOS transistors in sub-threshold region. This two-stage op-amp is designed using the Silterra 130nm technology library. The layout has been draw and its area had been calculated. The proposed two stage op-amp consists of NMOS current mirror as bias circuit, differential amplifier as the first stage and common source amplifier as the second stage. The first stage of an op-amp contributed high gain while the second stage contributes a moderate gain. The results show that the circuit is able to work at 1.8V power supply voltage (VDD) and provides gain of 69.73dB and 28.406MHz of gain bandwidth product for a load of 2pF capacitor. Therefore, the power dissipation and the consistency of this operational amplifier are better than previously reported operational amplifier

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110