Per-Core DVFS with Switched-Capacitor Converters for Energy Efficiency in Manycore Processors

Integrating multiple power converters on-chip improves energy efficiency of manycore architectures. Switched-capacitor (SC) dc-dc converters are compatible with conventional CMOS processes, but traditional implementations suffer from limited conversion efficiency. We propose a dynamic voltage and frequency scaling scheme with SC converters that achieves high converter efficiency by allowing the output voltage to ripple and having the processor core frequency track the ripple. Minimum core energy is achieved by hopping between different converter modes and tuning body-bias voltages. A multicore processor model based on a 28-nm technology shows conversion efficiencies of 90% along with over 25% improvement in the overall chip energy efficiency

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices

Switched Capacitor Voltage Converter

This project supports IoT development by reducing the power con- sumption and physical footprint of voltage converters. Our switched- capacitor IC design steps down an input of 1:0 - 1:4 V to 0:6 V for a decade of load current from 5 - 50A

Effect of CMOS Technology Scaling on Fully-Integrated Power Supply Efficiency

International audienceIntegrating a power supply in the same die as the powered circuits is an appropriate solution for granular, fine and fast power management. To allow same-die co-integration, fully integrated DC-DC converters designed in the latest CMOS technologies have been greatly studied by academics and industrialists in the last decade. However, there is little study concerning the effects of the CMOS scaling on these particular circuits. To show the trends, this paper compares the achievable efficiencies of the 2:1 switched capacitor DC-DC converter topology under the same constraints in 65, 130 and 350nm bulk CMOS nodes and 28nm in bulk and FDSOI technologies with various capacitor options

Design Space Evaluation for Resonant and Hard-charged Switched Capacitor Converters

USB Power Delivery enables a fixed ratio converter to operate over a wider range of output voltages by varying the input voltage. Of the DC/DC step-down converters powered from this type of USB, the hard-charged Switched Capacitor circuit is of interest to industry for its potential high power density. However implementation can be limited by circuit efficiency. In fully resonant mode, the efficiency can be improved while also enabling current regulation. This expands the possible applications into battery chargers and eliminates the need for a two-stage converter.In this work, the trade-off in power loss and area between the hard-charged and fully resonant switched capacitor circuit is explored using a technique that remains agnostic to inductor technology. The loss model for each converter is presented as well as discussion on the restrained design space due to parasitics in the passive components. The results are validated experimentally using GaN-based prototype converters and the respective design spaces are analyzed

Modeling and Efficiency Analysis of Multi-Phase Resonant Switched Capacitive Converters

International audienceThis paper presents an analytical method to evaluate pertinent data of the resonant capacitive switching converter especially the voltage gain and power efficiency. Instead of long transient simulation time, the proposed model uses frequency decomposition to speed-up computation. This method is valid for N-phase operation and extends the recently published studies on this promising topology outside zero-current/voltage switching conditions. Thanks to this tractable expression, we also reveal the intrinsic efficiencies over the voltage gain of 2-and 3-phase structures working at the resonant frequency in step-down operation. These results help to gain better understanding of multi-phase operation and encourage additional studies to use the full capability offered by the resonant switched capacitor converter especially for power on-chip integration. Keywords— DC-DC converter; switched-mode power supplies; resonant

Analysis and Design of a Hybrid Dickson Switched Capacitor Converter for Intermediate Bus Converter Applications

By 2020 it is predicted that 1/3 of all data will pass through the cloud. With society\u27s growing dependency on data, it is vital that data centers, the cloud\u27s physical house of content, operate with optimal energy performance to reduce operating costs.Unfortunately, today\u27s data centers are inefficient, both economically and environmentally. This has led to an increase in demand for energy-efficient servers. One opportunity for improved efficiency is in the power delivery architecture which delivers power from the grid to the motherboard. In this dissertation, the main focus is the intermediate bus converter (IBC), used for the intermediate conversion, typically 48-12V/5V, in server power supplies. The IBC requires compact design so that it can be placed as close to the load as possible to enable more space for computing power and high efficiency to reduce the need for external cooling. Most commonly used converter topologies today include expensive bulky magnetics hindering the converter\u27s power density. Furthermore, high output current of an IBC makes the efficiency very sensitive to any resistance, such as magnetic parasitic resistance or PCB trace resistance. In this work, analytical loss models are used to review the advantages and disadvantages of frequently used IBC topologies such as the phase-shifted full bridge and LLC. The Hybrid Dickson Switched Capacitor (HDSC) topology is also analyzed. The HDSC\u27s high step-down conversion ratio and low dependence on magnetics due to the reduced applied volt-seconds, provides a new opportunity for applications such as the intermediate bus converter. The HDSC designs the on-time of devices in order to achieve soft-charging between flying capacitors. Other advantages of the HDSC include low switch stress, small magnetics and adjustable duty cycle for voltage regulation. Challenges, such as minimizing parasitic inductance and resistance between flying capacitors, are addressed and recommendations for PCB layout are provided. In this paper, a 4:1 24-5V and 8:1 48-5V, 100W GaN-based HDSC is designed and tested. The influences of capacitor mismatch and limitations placed on soft-charging operation for the HDSC is also modeled. This analysis can be used as a tool for designers when selecting flying capacitors

A practical approach for magnetic core-loss characterization

A practical approach for magnetic core-loss characterization up to a few megahertz is presented. An error analysis is for the first time performed, revealing that corrections are needed to compensate for errors introduced by the extra phase shift inherent in a measurement setup, and by shunt parasitic capacitance associated with an inductive device under test. A simple technique is then proposed to control the error so as to satisfy prescribed tolerances. Extensive measurements done on a TDK PC40 core yield results which support the analysis. Several sample cores are then characterized at a few megahertz

Evaluation and implementation of a 5-level hybrid DC-DC converter

In this work, a hybrid voltage regulator topology is analyzed, implemented, and evaluated. The common topologies of DC-DC converters have proven to be lacking in some aspects, such as integrability for buck converters, or maximum efficiency for switched-capacitor regulators. The hybrid topology tackles these shortcomings by combining the advantages of switched-capacitor and inductor-based voltage regulators. A 5-level buck converter is evaluated, implemented, and compared to other converter implementations using the same components. The 5-Level Buck converter can achieve 5 different levels, allowing it to cover 4 operation regions, each between 2 levels. Accordingly, it covers a wide range of output voltages. By reducing the voltage difference at the inductor input, the 5-level buck converter can use smaller inductor compared to both 3-level and conventional buck converters which makes it cheaper, smaller in size, and much more efficient. Simulations show proper functionality of the 5-Level topology, while putting restrictions on the inductor size, efficiency, and component footprint (or total converter area). A test PCB is implemented for verification of the functionality and experimental measurements show that for the same switching frequency and inductor size, the 5-level buck converter achieves up to 15% efficiency improvement over a conventional buck converter and a 3-level buck converter at certain output voltage ranges. Peak efficiency of 94% has been achieved by the 5-Level hybrid converter, which includes all external switching and conduction losses. The proposed hybrid topology proved to yield high conversion efficiency even in the face of component size limitations, which indicates potential benefit in using multilevel converters for several off-chip as well as on-chip applications