Impact of RTN on Pattern Recognition Accuracy of RRAM-based Synaptic Neural Network

Resistive switching memory devices can be categorized into either filamentary or non-filamentary ones depending on the switching mechanisms. Both types have been investigated as novel synaptic devices in hardware neural networks, but there is a lack of comparative study between them, especially in random telegraph noise (RTN) which could induce large resistance fluctuations. In this work, we analyze the amplitude and occurrence rate of RTN in both Ta2O5 filamentary and TiO2/a-Si (a-VMCO) non-filamentary RRAM devices and evaluate its impact on the pattern recognition accuracy of neural networks. It is revealed that the non-filamentary RRAM has a tighter RTN amplitude distribution and much lower RTN occurrence rate than its filamentary counterpart which leads to negligible RTN impact on recognition accuracy, making it a promising candidate in synaptic application

Spiking Neural Networks for Inference and Learning: A Memristor-based Design Perspective

On metrics of density and power efficiency, neuromorphic technologies have the potential to surpass mainstream computing technologies in tasks where real-time functionality, adaptability, and autonomy are essential. While algorithmic advances in neuromorphic computing are proceeding successfully, the potential of memristors to improve neuromorphic computing have not yet born fruit, primarily because they are often used as a drop-in replacement to conventional memory. However, interdisciplinary approaches anchored in machine learning theory suggest that multifactor plasticity rules matching neural and synaptic dynamics to the device capabilities can take better advantage of memristor dynamics and its stochasticity. Furthermore, such plasticity rules generally show much higher performance than that of classical Spike Time Dependent Plasticity (STDP) rules. This chapter reviews the recent development in learning with spiking neural network models and their possible implementation with memristor-based hardware

AND-형 플래시 메모리 어레이를 활용한 하드웨어 기반 스파이킹 뉴럴 네트워크 구현

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 이종호.Neuromorphic engineering aims to implement a brain-inspired computing architecture as an alternative paradigm to the von Neumann processor. In this work, hardware-based neural networks that enable on-chip training using a thin-film transistor-type AND flash memory array architecture are designed. The synaptic device constituting the array is characterized by a doped p-type body, a gate insulator stack composed of SiO2 / Si3N4 / Al2O3, and a partially curved poly-Si channel. The p-body reduces the circuit burden on the high voltage driver required for both the source and drain lines when changing the synaptic weights. The high-κ material included in the gate insulator stack helps to lower the operating voltage of the device. As the device scales down, the structural characteristics of the device have the potential to increase the efficiency of the memory operation and the immunity to the voltage drop effect that occurs in the bit-lines of the array. In the AND array architecture using fabricated synaptic devices, a pulse scheme for selective memory operation is proposed and verified experimentally. Based on the measured characteristics of the fabricated synaptic devices and arrays, we design two types of hardware-based spiking neural networks (SNNs) according to the learning purpose. First, we propose a hardware-based SNN for unsupervised learning with spiking-timing-dependent plasticity (STDP) learning rule. The designed network does not use the pulses generated by the external circuitry, but the necessary pulses are generated in each spike neuron circuit. In this architecture, the STDP rule is implemented by the effective pulse scheme for using poly-silicon AND arrays. With the proposed pulse scheme and SNN, 91.63% of recognition accuracy is obtained in MNIST handwritten digit pattern learning using 200 output neurons. Second, we propose a hardware-based SNN for supervised learning with a direct feedback alignment (DFA) learning rule. Due to the DFA algorithm, which does not need to have the same synaptic weight in the forward path and backward path, the AND array architecture can be utilized in designing an efficient on-chip training neural network. Pulse schemes suitable for the proposed AND array architecture are also devised to implement the DFA algorithm in neural networks. In the system-level simulation, the recognition accuracy of up to 97.01% is obtained in the MNIST pattern learning task based on the proposed pulse scheme and computing architecture. In addition, we propose and verify the integration fabrication method of the proposed synaptic array and complementary metal-oxide-semiconductor (CMOS) circuits. Here, the CMOS circuits include either an integrate-and-fire circuit or a circuit that can change the width or amplitude of the spike signal. The proposed integration fabrication method has the advantage of reducing the number of masks and steps due to the shared process of the synaptic array and CMOS circuit. The proposed integration fabrication method is significant because it presents a methodology for efficient implantation of hardware-based neural networks as well as verification of excellent compatibility of the proposed synaptic device with CMOS.뉴로모픽 기술은 폰 노이만 프로세서의 대안으로서 두뇌에서 영감을 받은 컴퓨팅 아키텍처를 구현하는 것을 목표로 한다. 이 논문에서는 박막 트랜지스터형 및 플래시 메모리 어레이 아키텍처를 사용하여 온칩 훈련을 가능하게 하는 하드웨어 기반 신경망을 설계한다. 어레이를 구성하는 시냅스 소자는 도핑된 p형 바디, SiO2 / Si3N4 / Al2O3로 구성된 게이트 절연막 스택 및 부분적으로 구부러진 폴리실리콘 채널을 특징으로 한다. 시냅스 소자 구조에 포함된 바디 영역은 시냅스 가중치를 변경할 때 소스 및 드레인 라인 모두에 필요한 고전압 드라이버의 회로 부담을 줄일 수 있다. 또한 게이트 절연막 스택에 포함된 high- κ 물질은 시냅스 소자의 동작 전압을 낮출 수 있다. 시냅스 소자의 크기가 축소됨에 따라 소자의 구조적인 특징은 메모리 동작의 효율성 뿐만 아니라 어레이의 비트 라인에서 발생하는 전압 강하 효과에 대한 내성을 증가시킨다. 우리는 제작된 시냅스 소자를 이용한 AND형 어레이 구조에서 선택적인 메모리 동작을 위한 펄스 방식을 제안하고 실험적으로 검증한다. 이후 제작된 시냅스 소자 및 어레이의 측정된 특성을 기반으로 학습 목적에 따라 2가지 유형의 하드웨어 기반 스파이크 신경망 (SNN)을 설계한다. 먼저 스파이크 시점 의존 가소성 기반 학습 규칙을 이용하여 비지도 학습을 위한 하드웨어 기반 SNN을 제안한다. 설계된 네트워크는 외부 회로에서 펄스를 생성하지 않으며 각 스파이크 뉴런 회로에서 필요한 펄스들이 생성된다. 이러한 네트워크에서 스파이크 시점 의존 가소성 기반 학습 규칙은 폴리실리콘 AND형 어레이를 사용하기 위한 효과적인 펄스 구동 방식을 통해 구현된다. 제안된 펄스 구동 방식과 SNN을 기반으로 200개의 출력 뉴런을 사용하는 MNIST 필기 숫자 패턴 학습에서 91.63 %의 인식 정확도를 얻을 수 있다. 두 번째로, 우리는 직접 피드백 정렬 학습 규칙을 사용하여 지도 학습을 위한 하드웨어 기반 SNN을 제안한다. 순방향 경로와 역방향 경로에서 동일한 시냅스 가중치를 가질 필요가 없는 직접 피드백 정렬 알고리즘으로 인해 AND형 어레이 아키텍처는 효율적인 온칩 훈련 신경망 설계에 활용될 수 있다. AND형 어레이 아키텍처에 적합한 펄스 구동 방식도 신경망에서 직접 피드백 정렬 알고리즘을 구현하기 위해 고안된다. 시스템 수준 시뮬레이션에서 제안된 펄스 구동 방식과 컴퓨팅 아키텍처를 기반으로 하는 MNIST 패턴 학습에서 최대 97.01%의 인식 정확도를 얻을 수 있다. 또한, 우리는 제안된 시냅스 어레이와 CMOS 회로의 집적 공정 과정을 제안하고 이를 검증한다. 제안하는 집적 공정 방법은 시냅스 어레이와 CMOS 회로의 공정 과정을 공유함으로써 마스크와 공정 수를 줄일 수 있는 장점이 있다. 제안된 집적 공정 방법은 제안하는 시냅스 소자와 CMOS와의 우수한 호환성을 검증할 뿐만 아니라, 하드웨어 기반 신경망을 효율적으로 구현할 수 있는 방법론을 제시한다는 점에서 의의를 갖는다.Abstract i Contents iv List of Figures viii List of Tables xxvi 1. Introduction 1 1.1 Neuromorphic computing 1 1.2 Hardware-based spiking neural network 5 1.3 Purpose of research 8 1.4 Dissertation outline 11 2. TFT-type AND flash memory array 12 2.1 Device structure and fabrication 12 2.2 Characteristics of the device 17 2.3 Measurement results as a synaptic device 22 2.4 Measurement results as a synaptic array 33 3. Hardware-based SNN for unsupervised learning 48 3.1 SNN using spike-timing-dependent plasticity (STDP) 48 3.2 Pulse scheme for STDP learning rule 54 3.3 MNIST pattern learning and classification 62 4. Hardware-based SNN for supervised learning 67 4.1 SNN using direct feedback alignment (DFA) 67 4.2 Pulse scheme for DFA learning rule 73 4.3 MNIST pattern learning and classification 81 5. Hardware implementation of neural networks 86 5.1 Integration of a synaptic array and CMOS circuits 86 5.2 Measurement results of a synaptic array 101 5.3 Measurement results of CMOS circuits 115 6. Conclusion 139 Appendix A. Neuron circuits to implement a hardware-based neural network using the STDP learning algorithm and the pulse scheme not including the inhibition pulses 142 Appendix B. Neuron circuits to implement a hardware-based neural network using the STDP learning algorithm and the pulse scheme including the inhibition pulses 158 Bibliography 172 Abstract in Korean 181 List of Publications 183박

Chalcogenide and metal-oxide memristive devices for advanced neuromorphic computing

Energy-intensive artificial intelligence (AI) is prevailing and changing the world, which requires energy-efficient computing technology. However, traditional AI driven by von Neumann computing systems suffers from the penalties of high-energy consumption and time delay due to frequent data shuttling. To tackle the issue, brain-inspired neuromorphic computing that performs data processing in memory is developed, reducing energy consumption and processing time. Particularly, some advanced neuromorphic systems perceive environmental variations and internalize sensory signals for localized in-senor computing. This methodology can further improve data processing efficiency and develop multifunctional AI products. Memristive devices are one of the promising candidates for neuromorphic systems due to their non-volatility, small size, fast speed, low-energy consumption, etc. In this thesis, memristive devices based on chalcogenide and metal-oxide materials are fabricated for neuromorphic computing systems. Firstly, a versatile memristive device (Ag/CuInSe2/Mo) is demonstrated based on filamentary switching. Non-volatile and volatile features are coexistent, which play multiple roles of non-volatile memory, selectors, artificial neurons, and artificial synapses. The conductive filaments’ lifetime was controlled to present both volatile and non-volatile behaviours. Secondly, the sensing functions (temperature and humidity) are explored based on Ag conductive filaments. An intelligent matter (Ag/Cu(In, Ga)Se2/Mo) endowing reconfigurable temperature and humidity sensations is developed for sensory neuromorphic systems. The device reversibly switches between two states with differentiable semiconductive and metallic features, demonstrating different responses to temperature and humidity variations. Integrated devices can be employed for intelligent electronic skin and in-sensor computing. Thirdly, the memristive-based sensing function of light was investigated. An optoelectronic synapse (ITO/ZnO/MoO3/Mo) enabling multi-spectrum sensitivity for machine vision systems is developed. For the first time, this optoelectronic synapse is practical for front-end retinomorphic image sensing, convolution processing, and back-end neuromorphic computing. This thesis will benefit the development of advanced neuromorphic systems pushing forward AI technology