625 research outputs found

    End-of-Life and Constant Rate Reliability Modeling for Semiconductor Packages Using Knowledge-Based Test Approaches

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    End-of-life and constant rate reliability modeling for semiconductor packages are the focuses of this dissertation. Knowledge-based testing approaches are applied and the test-to-failure approach is approved to be a reliable approach. First of all, the end-of-life AF models for solder joint reliability are studied. The research results show using one universal AF model for all packages is flawed approach. An assessment matrix is generated to guide the application of AF models. The AF models chosen should be either assessed based on available data or validated through accelerated stress tests. A common model can be applied if the packages have similar structures and materials. The studies show that different AF models will be required for SnPb solder joints and SAC lead-free solder joints. Second, solder bumps under power cycling conditions are found to follow constant rate reliability models due to variations of the operating conditions. Case studies demonstrate that a constant rate reliability model is appropriate to describe non solder joint related semiconductor package failures as well. Third, the dissertation describes the rate models using Chi-square approach cannot correlate well with the expected failure mechanisms in field applications. The estimation of the upper bound using a Chi-square value from zero failure is flawed. The dissertation emphasizes that the failure data is required for the failure rate estimation. A simple but tighter approach is proposed and provides much tighter bounds in comparison of other approaches available. Last, the reliability of solder bumps in flip chip packages under power cycling conditions is studied. The bump materials and underfill materials will significantly influence the reliability of the solder bumps. A set of comparable bump materials and the underfill materials will dramatically improve the end-of-life solder bumps under power cycling loads, and bump materials are one of the most significant factors. Comparing to the field failure data obtained, the end-of-life model does not predict the failures in the field, which is more close to an approximately constant failure rate. In addition, the studies find an improper underfill material could change the failure location from solder bump cracking to ILD cracking or BGA solder joint failures

    Time integration damage model for Sn3.5Ag solder interconnect in power electronic module

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    In this study, existing damage evolution models in the literature for solder layer in microelectronics have been reviewed. A two dimensional approximate semi-analytic time integration damage indicator model for Sn3.5Ag material solder interconnect in power electronic module has been proposed. The proposed time dependent damage model is dependent on the inelastic strain, the accumulated damage at previous time step and the temperature. The strains were approximated semi-analytically. A numerical modelling methodology combined with the data from public domain for crack initiation and crack propagation of Sn3.5Ag solder layer has been adopted to extract the parameter values of the proposed damage model. The proposed model has advantages over fatigue lifetime models as it instantaneously predicts the damage over time for any loading history. The damage model was compared with Ansys FEA tool based damage prediction using Coffin Manson and Paris law fatigue models. The predicted damage value by the model is slightly higher than those models. Furthermore, this damage model does not need a time consuming numerical simulation evaluating the damage model variables, which is an advantag

    Enabling More than Moore: Accelerated Reliability Testing and Risk Analysis for Advanced Electronics Packaging

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    For five decades, the semiconductor industry has distinguished itself by the rapid pace of improvement in miniaturization of electronics products-Moore's Law. Now, scaling hits a brick wall, a paradigm shift. The industry roadmaps recognized the scaling limitation and project that packaging technologies will meet further miniaturization needs or ak.a "More than Moore". This paper presents packaging technology trends and accelerated reliability testing methods currently being practiced. Then, it presents industry status on key advanced electronic packages, factors affecting accelerated solder joint reliability of area array packages, and IPC/JEDEC/Mil specifications for characterizations of assemblies under accelerated thermal and mechanical loading. Finally, it presents an examples demonstrating how Accelerated Testing and Analysis have been effectively employed in the development of complex spacecraft thereby reducing risk. Quantitative assessments necessarily involve the mathematics of probability and statistics. In addition, accelerated tests need to be designed which consider the desired risk posture and schedule for particular project. Such assessments relieve risks without imposing additional costs. and constraints that are not value added for a particular mission. Furthermore, in the course of development of complex systems, variances and defects will inevitably present themselves and require a decision concerning their disposition, necessitating quantitative assessments. In summary, this paper presents a comprehensive view point, from technology to systems, including the benefits and impact of accelerated testing in offsetting risk

    Multiobjective design optimization of IGBT power modules considering power cycling and thermal cycling

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    Insulated-gate bipolar transistor (IGBT) power modules find widespread use in numerous power conversion applications where their reliability is of significant concern. Standard IGBT modules are fabricated for general-purpose applications while little has been designed for bespoke applications. However, conventional design of IGBTs can be improved by the multiobjective optimization technique. This paper proposes a novel design method to consider die-attachment solder failures induced by short power cycling and baseplate solder fatigue induced by the thermal cycling which are among major failure mechanisms of IGBTs. Thermal resistance is calculated analytically and the plastic work design is obtained with a high-fidelity finite-element model, which has been validated experimentally. The objective of minimizing the plastic work and constrain functions is formulated by the surrogate model. The nondominated sorting genetic algorithm-II is used to search for the Pareto-optimal solutions and the best design. The result of this combination generates an effective approach to optimize the physical structure of power electronic modules, taking account of historical environmental and operational conditions in the field

    MICROELECTRONICS PACKAGING TECHNOLOGY ROADMAPS, ASSEMBLY RELIABILITY, AND PROGNOSTICS

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    This paper reviews the industry roadmaps on commercial-off-the shelf (COTS) microelectronics packaging technologies covering the current trends toward further reducing size and increasing functionality. Due tothe breadth of work being performed in this field, this paper presents only a number of key packaging technologies. The topics for each category were down-selected by reviewing reports of industry roadmaps including the International Technology Roadmap for Semiconductor (ITRS) and by surveying publications of the International Electronics Manufacturing Initiative (iNEMI) and the roadmap of association connecting electronics industry (IPC). The paper also summarizes the findings of numerous articles and websites that allotted to the emerging and trends in microelectronics packaging technologies. A brief discussion was presented on packaging hierarchy from die to package and to system levels. Key elements of reliability for packaging assemblies were presented followed by reliabilty definition from a probablistic failure perspective. An example was present for showing conventional reliability approach using Monte Carlo simulation results for a number of plastic ball grid array (PBGA). The simulation results were compared to experimental thermal cycle test data. Prognostic health monitoring (PHM) methods, a growing field for microelectronics packaging technologies, were briefly discussed. The artificial neural network (ANN), a data-driven PHM, was discussed in details. Finally, it presented inter- and extra-polations using ANN simulation for thermal cycle test data of PBGA and ceramic BGA (CBGA) assemblies

    Design of Experiment Analysis of an Electronics Package Lid Using Finite Element Analysis

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    A design of experiment analysis is reported on data from warpage simulations using finite element analysis of a lidded electronics package. Warpage in a lid of an optical electronics package can detrimentally affect the reliability of the package as well as its optical performance. The present study focuses on the variety of materials and designs of lids relevant to recent technologies in electronics packaging. The finite element analysis (FEA) formulation in this study accurately predicts deformation and warpage in the elastic region with optimal computational time achieved through a choice of boundary conditions and mesh sensitivity studies. The results from FEA are compared to analytical calculations made using the classical laminate plate theory (CLPT) as well as the modified Suhir’s theory. It is observed that FEA results are more accurate as they account for the performance of die attach/ underfill materials regardless of the small thickness of the layer. The FEA data are finally used to conduct a design of experiments (DOE) analysis to investigate the influence of 3 distinct designs and 6 material choices on warpage of a lid. The analysis indicates that there is no significant interaction between the two parameters expected to affect the warpage in the lid. Material properties of the lid are found to have a greater effect on the warpage of the lid as compared to variabilities introduced in lid designs in this study. The FEA simulations performed consider only material behavior within the elastic limit and, in some situations, plastic deformation may occur which is more permanent and as such requires a more comprehensive analysis in the plastic region to enhance the data set for DOE studies

    Lifetime Estimation of IGBTs in a Grid-connected STATCOM

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    Lifetime estimation of power semiconductor devices, and IGBT devices in particular, used in the power electronics integrated with power systems has gained technical importance in recent times with increased scope of distributed generation, renewable energy systems and FACTS. Since most of the common failures (wire bond and solder fatigue) are caused by thermo-mechanical stresses, the methodology of lifetime estimation starts with temperature estimation, cycle counting based on rainflow algorithm, and finally degradation calculation based on linear accumulation model. Different number of RC cells for each packaging layer in the module for the thermal model, including the influence of encapsulant is proposed for temperature estimation of IGBTs in power modules. A modified rainflow algorithm with faster execution time and time dependent temperature calculation is introduced for cycle counting. Finally, the lifetime of the IGBT is estimated during STATCOM operation using real-time load profiles for power factor variation. For a power factor variation data for a building, the lifetime is estimated to be about 3 years. Similarly, a month long arc furnace load data is considered to compare the equivalent temperature based calculation to conventional tests. 4% more degradation is observed in the equivalent temperature based calculation than compared with conventional rainflow algorithm. A simulation study on the operation parameter dependence on the stresses in a wire is considered to estimate lifetime from Finite Element Analysis (FEA) in COMSOL. Power cycling tests are conducted on two different modules (600 V, 50 A H-bridge module and a 1200 V, 150 A phase leg module) to validate the lifetime model for four months. The low power module was tested without any protection circuits and hence failed catastrophically. Wire melt-off or fusing failure was dominantly observed, following by dielectric based short circuit failure. The high power module was tested with protection circuits to prevent catastrophic damage for a maximum of 4 months. A maximum of 20% degradation in static characteristics, with decreased on state resistance was observed in the modules. The degradation is attributed to increased junction temperature as the thermal resistance increases owing to solder fatigue

    Combining business process and failure modelling to increase yield in electronics manufacturing

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    The prediction and capturing of defects in low-volume assembly of electronics is a technical challenge that is a prerequisite for design for manufacturing (DfM) and business process improvement (BPI) to increase first-time yields and reduce production costs. Failures at the component-level (component defects) and system-level (such as defects in design and manufacturing) have not been incorporated in combined prediction models. BPI efforts should have predictive capability while supporting flexible production and changes in business models. This research was aimed at the integration of enterprise modelling (EM) and failure models (FM) to support business decision making by predicting system-level defects. An enhanced business modelling approach which provides a set of accessible failure models at a given business process level is presented in this article. This model-driven approach allows the evaluation of product and process performance and hence feedback to design and manufacturing activities hence improving first-time yield and product quality. A case in low-volume, high-complexity electronics assembly industry shows how the approach leverages standard modelling techniques and facilitates the understanding of the causes of poor manufacturing performance using a set of surface mount technology (SMT) process failure models. A prototype application tool was developed and tested in a collaborator site to evaluate the integration of business process models with the execution entities, such as software tools, business database, and simulation engines. The proposed concept was tested for the defect data collection and prediction in the described case study

    Finite Element Modeling of the Effect of Reflow Porosity on the Mechanical Behavior of Pb-free Solder Joints

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    abstract: Pb-free solders are used as interconnects in various levels of micro-electronic packaging. Reliability of these interconnects is very critical for the performance of the package. One of the main factors affecting the reliability of solder joints is the presence of porosity which is introduced during processing of the joints. In this thesis, the effect of such porosity on the deformation behavior and eventual failure of the joints is studied using Finite Element (FE) modeling technique. A 3D model obtained by reconstruction of x-ray tomographic image data is used as input for FE analysis to simulate shear deformation and eventual failure of the joint using ductile damage model. The modeling was done in ABAQUS (v 6.10). The FE model predictions are validated with experimental results by comparing the deformation of the pores and the crack path as predicted by the model with the experimentally observed deformation and failure pattern. To understand the influence of size, shape, and distribution of pores on the mechanical behavior of the joint four different solder joints with varying degrees of porosity are modeled using the validated FE model. The validation technique mentioned above enables comparison of the simulated and actual deformation only. A more robust way of validating the FE model would be to compare the strain distribution in the joint as predicted by the model and as observed experimentally. In this study, to enable visualization of the experimental strain for the 3D microstructure obtained from tomography, a three dimensional digital image correlation (3D DIC) code has been implemented in MATLAB (MathWorks Inc). This developed 3D DIC code can be used as another tool to verify the numerical model predictions. The capability of the developed code in measuring local displacement and strain is demonstrated by considering a test case.Dissertation/ThesisM.S. Mechanical Engineering 201
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