Comparative study of the MASH digital delta-sigma modulators

The paper focuses on the Multi-stAge noise SHaping (MASH) digital delta-sigma modulator (DDSM) that employs multi-moduli (MM-MASH). Different architectures of the MASH DDSM are compared. In particular, it is proven that a higherorder error feedback modulator (EFM) has the same sequence length as a first-order EFM (EFM1) in an MM-MASH. In addition, the method that is required to setup the quantisation moduli of the MM-MASH is introduced. The theory is validated by simulation

Design methodology for a maximum sequence length MASH digital delta-sigma modulator

The paper proposes a novel structure for a MASH digital delta-sigma modulator (DDSM) in order to achieve a long sequence length. The expression for the sequence length is derived. The condition to produce the maximum sequence length is also stated. It is proved that the modulator output only depends on the structure of the first-order error feedback modulator (EFM1) which is the first stage of a Multi-stAge noise SHaping (MASH) modulator

Mathematical analysis of prime modulus quantizer MASH digital delta-sigma modulator

A MASH digital delta-sigma modulator (DDSM) is analyzed mathematically. It incorporates first-order error feedback modulators (EFM) which include prime modulus quantizers to guarantee a minimum sequence length M. The purpose of this analysis is to calculate the exact sequence length of the aforementioned MASH DDSM. We show that the sequence length for an lth-order member of this modulator family is M for all constant inputs, and for all initial conditions, where M is the sequence length of the constituent first-order prime modulus quantizer EFMs.

Prediction of the Spectrum of a Digital Delta–Sigma Modulator Followed by a Polynomial Nonlinearity

This paper presents a mathematical analysis of the power spectral density of the output of a nonlinear block driven by a digital delta-sigma modulator. The nonlinearity is a memoryless third-order polynomial with real coefficients. The analysis yields expressions that predict the noise floor caused by the nonlinearity when the input is constant

Analysis, simulation and design of nonlinear RF circuits

The PhD project consists of two parts. The first part concerns the development of Computer Aided Design (CAD) algorithms for high-frequency circuits. Novel Padébased algorithms for numerical integration of ODEs as arise in high-frequency circuits are proposed. Both single- and multi-step methods are introduced. A large part of this section of the research is concerned with the application of Filon-type integration techniques to circuits subject to modulated signals. Such methods are tested with analog and digital modulated signals and are seen to be very effective. The results confirm that these methods are more accurate than the traditional trapezoidal rule and Runge-Kutta methods. The second part of the research is concerned with the analysis, simulation and design of RF circuits with emphasis on injection-locked frequency dividers (ILFD) and digital delta-sigma modulators (DDSM). Both of these circuits are employed in fractional-N frequency synthesizers. Several simulation methods are proposed to capture the locking range of an ILFD, such as the Warped Multi-time Partial Differential Equation (WaMPDE) and the Multiple-Phase-Condition Envelope Following (MPCENV) methods. The MPCENV method is the more efficient and accurate simulation technique and it is recommended to obviate the need for expensive experiments. The Multi-stAge noise Shaping (MASH) digital delta-sigma modulator (DDSM) is simulated in MATLAB and analysed mathematically. A novel structure employing multimoduli, termed the MM-MASH, is proposed. The goal in this design work is to reduce the noise level in the useful frequency band of the modulator. The success of the novel structure in achieving this aim is confirmed with simulations

The practical limits of MASH Delta-Sigma Modulators designed to maintain very long controllable sequence lengths for structured tone mitigation

The delta-sigma modulator (DSM) is an essential block for a Fractional-N (FN) frequency synthesizers and is used for generating the fractional part of the division ratio. Digital DSMs (DDSM) with rational input and rational initial conditions can be thought as Finite State Machines (FSM) and they always produce finite length sequences in accordance with the applied input. To provide smooth quantization noise power distribution (tone free) and to get rid of structured tones, the modulator should complete its cycle and return to initial starting state. This method is called maintaining controllable sequence length. In this paper, the practicality of this method will be investigated for DDSMs composed of up to 5th order MASH 1-1-1-1-1 structures by considering lock time requirements of the synthesizers designed for wireless transceiver applications such as GSM900, DCS-1800, UMTS(WCDMA),WLAN, ZigBee and Bluetooth

Structured tone mitigation in 3rd and 4th order MASH Delta-Sigma Modulators-comparative study

A delta-sigma modulator (DSM) can be thought as a nonlinear chaotic system that may exhibit tonal behaviour in its output spectrum. These tones are sometimes referred to as spurs and they are undesirable. To provide for the mitigation of structured tones, application of dithering, using chaotic modulators, loading irrational initial conditions and maintaining controllable maximum sequence lengths are commonly used and advised methods primarily in Multi-stAge noise SHaping (MASH) DSMs. Higher order MASH-DSMs are less problematic and are commonly used in many high speed and low noise frequency synthesiser circuits. As MASH is composed of cascaded first order digital DSM stages, it is unconditionally stable. In this paper, the tone mitigation techniques for MASH 1-1-1 and MASH 1-1-1-1 modulators are compared and their noise performances presented

Reduced complexity MASH delta-sigma modulator

A reduced complexity digital multi-stage noise shaping (MASH) delta-sigma modulator for fractional-N frequency synthesizer applications is proposed. A long word is used for the first modulator in a MASH structure; the sequence length is maximized by setting the least significant bit of the input to 1; shorter words are used in subsequent stages. Experimental results confirm simulation

Designing an Efficient WCDMA Compliant Fractional-N Frequency Synthesizer

In this paper, fractional-N PLL is introduced to generate 1.965 GHz according to WCDMA specification , where a proposed deterministic 4th order MASH structure that guarantees a long sequence length to be used with simple stochastic dithering at the last stage as a noise shaping technique achieving hardware budget compared with classical dithering that used long linear feedback shift register LFSR . Modulator in band phase noise is -100dBc/Hz within the loop bandwidth of 1MHz, the PLL lock time is less than 25 μs. C++ language is used in the simulation of the system behavior for all blocks of the synthesizer due to its flexibility and high speed of execution, then data is post processed using MATLAB R2011a. The proposed MASH structure consumes 89% FFs and 90% LUTs of the Dithered MASH reported in ref.[9] for identical number of bits achieve significant hardware cost reduction