The paper focuses on the Multi-stAge noise SHaping (MASH) digital delta-sigma modulator (DDSM) that employs multi-moduli (MM-MASH). Different architectures of the MASH DDSM are compared. In particular, it is proven that a higherorder error feedback modulator (EFM) has the same sequence length as a first-order EFM (EFM1) in an MM-MASH. In addition, the method that is required to setup the quantisation moduli of the MM-MASH is introduced. The theory is validated by simulation

Condon, Marissa

Xu, Tao

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Comparative study of the MASH digital delta-sigma modulators

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Comparative Study of the MASH DigitalDelta-Sigma ModulatorsTao XuSchool of Electronic EngineeringDublin City UniversityDublin 9, IrelandEmail: taoxu@eeng.dcu.ieMarissa CondonSchool of Electronic EngineeringDublin City UniversityDublin 9, IrelandEmail: condonm@eeng.dcu.ieAbstract—The paper focuses on the Multi-stAge noise SHaping(MASH) digital delta-sigma modulator (DDSM) that employsmulti-moduli (MM-MASH). Different architectures of the MASHDDSM are compared. In particular, it is proven that a higher-order error feedback modulator (EFM) has the same sequencelength as a first-order EFM (EFM1) in an MM-MASH. Inaddition, the method that is required to setup the quantisationmoduli of the MM-MASH is introduced. The theory is validatedby simulation.I. INTRODUCTIONDigital delta-sigma modulators (DDSM) are widely usedin consumer electronic equipment such as cellular telephones,MP3 players and wireless-LANs. A DDSM is composed ofseveral error feedback machines (EFM). The architectures ofEFMs decide the sequence length of DDSMs. Since a shortsequence length results in unwanted frequency components inthe output frequency spectrum [1], much research has beendone into maximising the sequence length. There are twoapproaches to lengthen the sequence length: stochastic anddeterministic methods. The most common stochastic approachis that of dithering [2] [3]. However, it requires extra hardwareand inherently introduces additional noise in the the useful fre-quency band. Thus, some deterministic design methodologieshave been proposed to maximise the sequence length.Borkowski [4] sets the initial condition of the registers tomake the sequence length of the conventional MASH DDSMreach its maximum value. Hosseini [5] modifies the structureof DDSMs to make the quantizer modulus a prime number.The period of such a sequence is proven by mathematicalanalysis [6]. Xu [7] introduces a digital delta-sigma modulatorstructure to further increase the sequence length. It proposesthat the modulus of each quantizer is set as a differentvalue from each other. Note that each quantizer has only onemodulus. Furthermore, all of the moduli are co-prime numbers.The difference between the co-prime numbers and the primenumbers [8] is stated as below:1) A prime number is a natural number which has exactlytwo divisors: 1 and itself.2) If the greatest common divisor of any two numbers is1, they are co-prime numbers. They do NOT have to beprime numbers.Fig. 1. MASH DDSM architecture.The hardware requirement is reduced, if the MASH DDSMutilises higher order EFMs [9]. However, it results in poorernoise performance. This paper examines the use of higher-order MM-EFMs. In section II, the different architectures ofthe EFM1s are introduced. Their sequence length is compared.In section III, the sequence length of higher-order MM-EFMsis derived. The simulation results are illustrated in section V.II. PREVIOUS WORK WITH EFM1SThe architecture of an lth order MASH DDSM is illustratedin Fig. 1. It contains l first-order error-feedback modulators(EFM1). x[n] and y[n] are an n0-bit input digital word and anm-bit output, respectively. The relationship between them ismean(y) =XM(1)where mean(y) represents the average value of y, X isthe decimal number corresponding to the digital sequencex[n] [10], i.e., x[n] = X ∈ {1, 2, ...,M − 1}, and M is thequantizer modulus which is set as 2n0 in the conventionalDDSM.A. Conventional EFM1The model of the EFM1 is shown in Fig. 2. This is a corecomponent in the make-up of the MASH digital delta-sigmamodulator (DDSM). The rectangle Z−1 represents the registerwhich stores the error e[n] and delays it for one time sample.Q(·) is the quantization function:y[n] = Q(u[n]) ={1, u[n] ≥ M0, u[n] < M (2)Fig. 2. EFM1: First-order error-feedback modulator.whereu[n] = x[n] + e[n− 1]. (3)The guaranteed and maximum sequence lengths for thisstructure have been found from simulations [4], and are asshown in Table I. To achieve both of these sequence lengths,the first stage EFM1 must have an odd initial condition.This is implemented by setting the register. The modulatorperiod varies between the guaranteed and maximum sequencelength dependent on the value of the input. It is found thatthe conventional MASH modulator period will always beapproximately equal to the maximum sequence length if thequantizer modulus, M, is set as a prime number [6].TABLE ITHE SEQUENCE LENGTH SUMMARISED IN [4].Modulator Order Guaranteed Period Maximum Period2 2n0−1 2n0+13 2n0+1 2n0+14 2n0+1 2n0+25 2n0+2 2n0+2B. HK-EFM1The architecture of the modified EFM1 used in the HK-MASH is illustrated in Fig. 3. The only difference between itand the conventional EFM1 in Fig. 2 is the presence of thefeedback block aZ−1. a is a specifically-chosen small integerto make (M − a) the maximum prime number below 2n0 [5].The sequence length of it is (2n0 − a)l ≈ (2n0)l.Fig. 3. The modified EFM1 used in HK-MASH.C. MM-EFM1The structure for the MASH digital delta-sigma modulator(DDSM) employing multi-moduli [7] is reviewed here. It isFig. 4. MM-EFM1: The modified first-order error-feedback modulator usedin MM-MASH.termed the MM-MASH. As illustrated in Fig. 4, Mp representsthe quantizer modulus in pth stage of MM-EFM1. The crucialpoints to note about this structure are:1) Every MM-EFM1 has a different modulus2) Each MM-EFM1 still only has ONE quantizer modulus.The sequence length of the pth effective stage EFM1depends on the previous EFM1 stage:Np∑k=1yp =KMpNp−1∑k=1ep−1 (4)whereK =NpNp−1. (5)The expression for the sequence length of the pth EFM1 inan lth order MASH modulator is:Np =M1M2...Miλp(6)where p ∈ {1, 2, 3, ..., l} and λp is the maximum commondivisor of λp−1Mp and M1M2...Mp−1mean(ep−1). Note thatwhen p = 1, mean(e0) = X and λ0 = M0 = 1.Then the lth order MASH DDSM sequence length isexpressed as:N =M1 ·M2 · ... ·Mlλ(7)where λ is a parameter to make N the least common multipleof the sequence length of each stage Ni.If the two conditions shown below are satisfied:C1: X and M1 are co-prime numbersC2: {M1, M2, ..., Ml} are co-prime numbersthe sequence length is maximised toNmax = M1 ·M2 · ... ·Ml. (8)D. Comparison of the Sequence LengthThe sequence length is only 1024 from a 9-bit conventionalMASH 1-1-1. The sequence lengths of the HK-MASH andthe MM-MASH are compared in Table II. The MM-MASHachieves a longer sequence when the word length is 8, 9, 10and 11, and hence is deemed superior.TABLE IIA COMPARISON OF THE SEQUENCE LENGTHS FOR THE HK-MASH ANDMM-MASH.Word length HK-MASH MM-MASH Difference8 bit 15.81× 106 16.39× 106 +0.58× 1069 bit 131.87× 106 133.17× 106 +1.3× 10610 bit 1.06× 109 1.07× 109 +10× 10611 bit 8.48× 109 8.55× 109 +70× 106Fig. 5. Higher order error-feedback modulator.III. THE ARCHITECTURE OF THE MM-EFMA. The Sequence Length of the MM-EFMThe structure of an mth order EFM (EFMm) is illustratedin Fig. 5. The symbols R1, R2, ..., Rm and A1, A2, ..., Amrepresent the initial condition and gain of the ith registers,respectively, where i ∈ {1, 2, ...,m}. The noise transferfunction isNTF =(Z − 1)mZm. (9)The value of the gains Ai is obtained as:m∑i=1AiZ−i = 1−NTF. (10)Now the calculation for the sequence length of a second-order EFM (EFM2) will be shown below as an example, sinceEFM2 is the most popular higher-order EFM in practice [4].The coefficients [A1, A2] are obtained from (10) as [2,−1].The EFM2 is assumed as the pth stage in a MASH DDSM.Thus the state variable u is dependent on the output of previousstage:up[1] = ep−1[1] + 2R1 −R2. (11)Using (11), the error is expressed asep[1] =up[1]−M · yp[1]=ep−1[1] + 2R1 −R2 −Mp · yp[1] (12)After several time steps, the values of the registers are changedfrom their initial conditions to ep. Thenep[2] =ep−1[2] + 2ep[1]−R2 −Mp · yp[2] (13)ep[3] =ep−1[3] + 2ep[2]− ep[1]−Mp · yp[3] (14)...ep[Np] =ep−1[Np] + 2ep[Np − 1]− ep[Np − 2]−Mp · yp[k].(15)The sum of all of the above equations (12)-(15) isNp∑k=1ep[k] =Np∑k=1ep−1[k] + 2Np−1∑k=0ep[k]−Np−2∑k=−1ep[k]−Mp ·Np∑k=1yp[k] (16)Since ep is periodic with the period Np [6] in the steady state,Np∑k=1ep[k] =Np−1∑k=0ep[k] =Np−2∑k=−1ep[k] (17)Then (16) becomesNp∑k=1yp =1MpNp∑k=1ep−1. (18)If the relationship between the sequence length of the pth and(p− 1)th stage EFM isNp = K ·Np−1 (19)(18) is modified toNp∑k=1yp =KMpNp−1∑k=1ep−1. (20)Obviously, (20) is the same as (4). Thus, the sequence lengthof the EFM2 is same as that of the EFM1, if both of themare the pth stage in a lth stage DDSM. In other words and thecrucial point, the sequence length of a MASH DDSM doesnot depend on the order level, but on the number of EFMs.For example, the period of MM-MASH 1-2 isN =M1 ·M2λ(21)where λ is a parameter to make N the least common multipleof N1 and N2. If the two conditions, C1 and C2, shown inSection II-C are satisfied, the maximum sequence length isN = M1 ·M2. (22)This is same as the period of the MM-MASH 1-1.B. The Setup of the Quantisation ModuliM1 is set as a prime number around 2n0 . This is to makeX and M1 always mutual prime numbers and therefore satisfyC1. This condition must be satisfied to maximise the sequencelength of the MASH DDSM and to make the sequence lengthindependent of the value of input. In order to maintain themodulator output accuracy, the value of the input DC X isadjusted toX = M1 ·mean(y) (23)where mean(y) is the required output to control the staticfrequency divider in a fractional-N frequency synthesizer.In an l stage MM-MASH, there are l co-prime numbersaround 2n0 that need to be found in order to satisfy C2. Thehigher the modulator order, the greater difficulty in findingsuitable values for these moduli. Fortunately, the most popularMASH DDSM in modern communication systems has only 2or 3 stages [4]. Note that all of the quantizer moduli shouldbe chosen no bigger than 2n0 to avoid necessitating extrahardware. Some quantizer moduli chosen by the authors for aMM-MASH contains 3 stages EFMs are given in Table III.TABLE IIISOME SAMPLE MODULI OF THE 3RD ORDER MM-MASH.Word length M1 M2 M38 bit 251 256 2559 bit 509 512 51110 bit 1021 1024 102311 bit 2039 2048 2047IV. SIMULATION RESULTSAll of the models of the EFM1, EFM and MASH are builtand simulated in Simulink. The autocorrelation function [4] isused to determine the sequence length of the MASH DDSM.As seen in Fig. 6, the sequence length of a 9-bit MM-MASH1-2 is 260608 and this equals M1 ·M2 as given in Table III.The power spectrum is compared to examine the noiseperformance of the various architectures. The power spectraldensity [11] of the 9-bit MM-MASH 1-1-1 and 9-bit MM-MASH 1-2 is compared in Fig. 7. Both of these are 3rd order.It is evident from the figure that the MM-MASH 1-1-1 has abetter noise performance than the MM-MASH 1-2. This is asexpected as the sequence length of the former is longer thanthat of the latter as shown in Section III-A. However, the MM-MASH 1-2 has the advantage on less hardware requirementsand so a balance between hardware cost and noise performanceis required in the selection of the most suitable structure.-4 -3 -2 -1 0 1 2 3 4x 10599.51010.511x 104Fig. 6. The autocorrelation result for the 9-bit MM-MASH 1-2.V. CONCLUSIONSThe structures of different MASH DDSMs are compared.The proposed MM-MASH has the longest sequence lengthand hence is advantageous from the perspective of noiseperformance. In this paper, the use of higher-order EFMs in theMM-MASH is investigated. The sequence length of the MM-MASH 1-1 is the same as the MM-MASH 1-2. It is shownthat the MM-MASH 1-1-1 has the better noise performanceFig. 7. The power spectral density of the dithered conventional MASHDDSM and non-dithered MM-MASH.than the MM-MASH 1-2. Both are 3rd order but the latterone requires less hardware. The decision regarding structurechoice is therefore a balance between the noise performancerequirements and the hardware requirements.ACKNOWLEDGEMENTThis material is based upon works supported by ScienceFoundation Ireland under Principal Investigator Grant No.05/IN.1/I18.REFERENCES[1] D. Reefman, J. Reiss, E. Janssen, and M. Sandler, “Description of limitcycles in sigma-delta modulators,” IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 52, no. 6, pp. 1211–1223, June 2005.[2] S. Pamarti, J. Welz and I. Galton, “Statistics of the Quantization Noise in1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators,” IEEETrans. on Circuits and Systems-I: Regular Papers, vol. 54, no. 3, pp.492–503, March 2007.[3] S. Pamarti and I. Galton, “LSB Dithering in MASH Delta-Sigma D/AConverters,” IEEE Trans. on Circuits and Systems-I: Regular Papers,vol. 54, no. 4, April 2007.[4] M. J. Borkowski, T. A. D. Riley, J. Ha¨kkinen, and J. Kostamovaara,“A Practical Δ − Σ Modulator Design Method Based on PeriodicalBehavior Analysis,” IEEE Trans. on Circuits and Systems-II: ExpressBriefs, vol. 52, no. 10, pp. 626–630, Oct. 2005.[5] K. Hosseini and M. P. Kennedy, “Maximum Sequence Length MASHDigital Delta-Sigma Modulators,” IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 54, no. 12, Dec. 2007.[6] K. Hosseini and M. P. Kennedy, “Mathematical Analysis of a PrimeModulus Quantizer MASH Digital Delta-Sigma Modulator,” IEEETrans. on Circuits and Systems-II: Express Brief, vol. 54, no. 12, Dec.2007.[7] T. Xu and M. Condon, “The MASH Digital Delta-Sigma Modulatorwith Multi-Moduli,” submitted to IET Circuits, Devices & Systems.[8] R. E. Crandall and C. Pomerance, Prime numbers: a computationalperspective, Springer, 2001.[9] L. Sun, T. Lepley, F. Nozahic, A. Bellissant, T. Kwasniewski and B.Heim, “Reduced Complexity, High Performance Digital Delta-SigmaModulator for Fractional-N Frequency Synthesis,” in Proc. IEEE Inter-national Symposium on Circuits and Systems, Orlando, USA, June 1999,vol.2, pp. 152-155.[10] M. J. Borkowski and J. Kostamovaara, “Spurious Tone Free DigitalDelta-Sigma Modulator Design for DC Inputs,” in Proc. IEEE Inter-national Symposium on Circuits and Systems, Kobe, Japan, May 2005,pp.5601–5604.[11] A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing.Upper Saddle River, NJ: Prentice-Hall, 1999.

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Comparative study of the MASH digital delta-sigma modulators

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