Otimização e melhoria da modulação comportamental para os interfaces de E/S analógica e de sinal misto de alta velocidade

Doutoramento em Engenharia ElectrotécnicaA integridade do sinal em sistemas digitais interligados de alta velocidade, e avaliada através da simulação de modelos físicos (de nível de transístor) é custosa de ponto vista computacional (por exemplo, em tempo de execução de CPU e armazenamento de memória), e exige a disponibilização de detalhes físicos da estrutura interna do dispositivo. Esse cenário aumenta o interesse pela alternativa de modelação comportamental que descreve as características de operação do equipamento a partir da observação dos sinais eléctrico de entrada/saída (E/S). Os interfaces de E/S em chips de memória, que mais contribuem em carga computacional, desempenham funções complexas e incluem, por isso, um elevado número de pinos. Particularmente, os buffers de saída são obrigados a distorcer os sinais devido à sua dinâmica e não linearidade. Portanto, constituem o ponto crítico nos de circuitos integrados (CI) para a garantia da transmissão confiável em comunicações digitais de alta velocidade. Neste trabalho de doutoramento, os efeitos dinâmicos não-lineares anteriormente negligenciados do buffer de saída são estudados e modulados de forma eficiente para reduzir a complexidade da modelação do tipo caixa-negra paramétrica, melhorando assim o modelo standard IBIS. Isto é conseguido seguindo a abordagem semi-física que combina as características de formulação do modelo caixa-negra, a análise dos sinais eléctricos observados na E/S e propriedades na estrutura física do buffer em condições de operação práticas. Esta abordagem leva a um processo de construção do modelo comportamental fisicamente inspirado que supera os problemas das abordagens anteriores, optimizando os recursos utilizados em diferentes etapas de geração do modelo (ou seja, caracterização, formulação, extracção e implementação) para simular o comportamento dinâmico não-linear do buffer. Em consequência, contributo mais significativo desta tese é o desenvolvimento de um novo modelo comportamental analógico de duas portas adequado à simulação em overclocking que reveste de um particular interesse nas mais recentes usos de interfaces de E/S para memória de elevadas taxas de transmissão. A eficácia e a precisão dos modelos comportamentais desenvolvidos e implementados são qualitativa e quantitativamente avaliados comparando os resultados numéricos de extracção das suas funções e de simulação transitória com o correspondente modelo de referência do estado-da-arte, IBIS.Signal integrity (SI) simulation of high-speed digital interconnected system via transistor level models is computational expensive (e.g. CPU time and memory storage), and requires the availability of physical details information of device’s internal structure. This scenario raises the interest for a behavioral modeling alternative which describes the device’s operation characteristics based on the observed input/output (I/O) electrical signal. I/O buffers that interface memory’s interconnects have major share in the computational load containing a very active complex functional part and high numbers of pins. Particularly, output buffers/drivers are forced to distort the I/O signals due to their nonlinear dynamics. In this concern, they constitute the integrated circuit (IC) bottleneck of ensuring reliable data transmission in the high-speed digital communication link. In this PhD work, the previously neglected driver’s nonlinear dynamic effects are efficiently captured to significantly reduce the state of the art black-box parametric modeling complexities and enhance the input/output buffers information specifications (IBIS). This is achieved by following the gray-box approach that merges the features of the black-box model’s formulation, the analysis of the observed I/O electrical signals and the buffer’s physical structure properties under practical operation conditions. This approach leads to physically inspired behavioral model’s construction procedure that overcomes the issues of the previous modeling approaches by optimizing the resources used at different model’s generation steps (i.e. characterization, formulation, extraction, and implementation) to mimic the driver’s nonlinear dynamic behavior. Moreover, the most important achievement is the development of a new two-port analog behavioral model for overclocking simulation that copes with the recent trends in I/O memory interfaces characterized by higher data rate transmission. The effectiveness and the accuracy of the developed and implemented behavioral models are qualitatively and quantitatively assessed by comparing the numerical results of their functions extraction and transient simulation to the ones simulated and extracted with transistor level models and the state of the art IBIS in order to validate their predictive and the generalization capabilities

Periodically Disturbed Oscillators

By controlling the timing of events and enabling the transmission of data over long distances, oscillators can be considered to generate the "heartbeat" of modern electronic systems. Their utility, however, is boosted significantly by their peculiar ability to synchronize to external signals that are themselves periodic in time. Although this fascinating phenomenon has been studied by scientists since the 1600s, models for describing this behavior have seen a disconnect between the rigorous, methodical approaches taken by mathematicians and the design-oriented, physically-based analyses carried out by engineers. While the analytical power of the former is often concealed by an inundation of abstract mathematical machinery, the accuracy and generality of the latter are constrained by the empirical nature of the ensuing derivations. We hope to bridge that gap here. In this thesis, a general theory of electrical oscillators under the influence of a periodic injection is developed from first principles. Our approach leads to a fundamental yet intuitive understanding of the process by which oscillators lock to a periodic injection, as well as what happens when synchronization fails and the oscillator is instead injection pulled. By considering the autonomous and periodically time-varying nature that underlies all oscillators, we build a time-synchronous model that is valid for oscillators of any topology and periodic disturbances of any shape. A single first-order differential equation is shown to be capable of making accurate, quantitative predictions about a wide array of properties of periodically disturbed oscillators: the range of injection frequencies for which synchronization occurs, the phase difference between the injection and the oscillator under lock, stable vs. unstable modes of locking, the pull-in process toward lock, the dynamics of injection pulling, as well as phase noise in both free-running and injection-locked oscillators. The framework also naturally accommodates superharmonic injection-locked frequency division, subharmonic injection-locked frequency multiplication, and the general case of an arbitrary rational relationship between the injection and oscillation frequencies. A number of novel insights for improving the performance of systems that utilize injection locking are also elucidated. In particular, we explore how both the injection waveform and the oscillator's design can be modified to optimize the lock range. The resultant design techniques are employed in the implementation of a dual-moduli prescaler for frequency synthesis applications which features low power consumption, a wide operating range, and a small chip area. For the commonly used inductor-capacitor (LC) oscillator, we make a simple modification to our framework that takes the oscillation amplitude into account, greatly enhancing the model's accuracy for large injections. The augmented theory uniquely captures the asymmetry of the lock range as well as the distinct characteristics exhibited by different types of LC oscillators. Existing injection locking and pulling theories in the available literature are subsumed as special cases of our model. It is important to note that even though the veracity of our theoretical predictions degrades as the size of the injection grows due to our framework's linearization with respect to the disturbance, our model's validity across a broad range of practical injection strengths are borne out by simulations and measurements on a diverse collection of integrated LC, ring, and relaxation oscillators. Lastly, we also present a phasor-based analysis of LC and ring oscillators which yields a novel perspective into how the injection current interacts with the oscillator's core nonlinearity to facilitate injection locking.</p

Analog-Digital System Modeling for Electromagnetic Susceptibility Prediction

The thesis is focused on the noise susceptibility of communication networks. These analog-mixed signal systems operate in an electrically noisy environment, in presence of multiple equipments connected by means of long wiring. Every module communicates using a transceiver as an interface between the local digital signaling and the data transmission through the network. Hence, the performance of the IC transceiver when affected by disturbances is one of the main factors that guarantees the EM immunity of the whole equipment. The susceptibility to RF and transient disturbances is addressed at component level on a CAN transceiver as a test case, highlighting the IC features critical for noise immunity. A novel procedure is proposed for the IC modeling for mixed-signal immunity simulations of communication networks. The procedure is based on a gray-box approach, modeling IC ports with a physical circuit and the internal links with a behavioural block. The parameters are estimated from time and frequency domain measurements, allowing accurate and efficient reproduction of non-linear device switching behaviours. The effectiveness of the modeling process is verified by applying the proposed technique to a CAN transceiver, involved in a real immunity test on a data communication link. The obtained model is successfully implemented in a commercial solver to predict both the functional signals and the RF noise immunity at component level. The noise immunity at system level is then evaluated on a complete communication network, analyzing the results of several tests on a realistic CAN bus. After developing models for wires and injection probes, a noise immunity test in avionic environment is carried out in a simulation environment, observing good overall accuracy and efficiency

Behavioural simulation of mixed analogue/digital circuits.

Continuing improvements in integrated circuit technology have made possible the implementation of complex electronic systems on a single chip. This often requires both analogue and digital signal processing. It is essential to simulate such IC's during the design process to detect errors at an early stage. Unfortunately, the simulators that are currently available are not well-suited to large mixed-signal circuits. This thesis describes the design and development of a new methodology for simulating analogue and digital components in a single, integrated environment. The methodology represents components as behavioural models that are more efficient than the circuit models used in conventional simulators. The signals that flow between models are all represented as piecewise-linear (PWL) waveforms. Since models representing digital and analogue components use the same format to represent their signals, they can be directly connected together. An object-oriented approach was used to create a class hierarchy to implement the component models. This supports rapid development of new models since all models are derived from a common base class and inherit the methods and attributes defined in their parentc lassesT. he signal objectsa re implementedw ith a similar class hierarchy. The development and validation of models representing various digital, analogue and mixed-signal components are described. Comparisons are made between the accuracy and performance of the proposed methodology and several commercial simulators. The development of a Windows-based demonstrations imulation tool called POISE is also described. This permitted models to be tested independently and multiple models to be connected together to form structural models of complex circuits

Method for Sizing MOS Transistors for VLSI

Determining the device width to length ratios has typically been an iterative process for the custom IC digital design engineer. After the logic design phase is complete for a particular circuit, the designer would make an educated guess at the device sizes. Then by trial and error, using SPICE or another circuit simulator, suitable sizes would be determined. Unfortunately, this approach is time consuming and the resulting sizes are often a good bit larger than they need to be to maintain a certain speed because of the lack of a rigorous sizing methodology. This paper describes a method for reducing the time in obtaining a CMOS circuit design by providing the designer with transistor sizes which yield consistent gate to gate propagation delays within a delay path. The technical justifications are developed and several test cases are synthesized to illustrate this method. Switching time accuracy is verified using SPICE and the automatically generated sizes. A program written in the Ada language to perform device sizing is discussed as well. The ramifications of area reduction are discussed as it pertains to custom and semicustom design methodologies. Algorithms to perform area minimization are presented along with other enhancements to the program

Advancement on the Susceptibility of Analog Front-Ends to EMI

L'abstract è presente nell'allegato / the abstract is in the attachmen

NASA SERC 1990 Symposium on VLSI Design

This document contains papers presented at the first annual NASA Symposium on VLSI Design. NASA's involvement in this event demonstrates a need for research and development in high performance computing. High performance computing addresses problems faced by the scientific and industrial communities. High performance computing is needed in: (1) real-time manipulation of large data sets; (2) advanced systems control of spacecraft; (3) digital data transmission, error correction, and image compression; and (4) expert system control of spacecraft. Clearly, a valuable technology in meeting these needs is Very Large Scale Integration (VLSI). This conference addresses the following issues in VLSI design: (1) system architectures; (2) electronics; (3) algorithms; and (4) CAD tools

MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR

As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G4FET [G4FET] is a SOI transistor with four independent gates. Although G4FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G4FET into a mainstream technology. The research goal is to develop suitable SPICE models for G4FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G4FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation. The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal–oxide–semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and provides good results compared to already demonstrated experimental works with innovative G4FET circuits. The final phase of this work involves the development of a physics-based compact model of G4FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G4FET

Design and Implementation of Switching Voltage Integrated Circuits Based on Sliding Mode Control

The need for high performance circuits in systems with low-voltage and low-power requirements has exponentially increased during the few last years due to the sophistication and miniaturization of electronic components. Most of these circuits are required to have a very good efficiency behavior in order to extend the battery life of the device. This dissertation addresses two important topics concerning very high efficiency circuits with very high performance specifications. The first topic is the design and implementation of class D audio power amplifiers, keeping their inherent high efficiency characteristic while improving their linearity performance, reducing their quiescent power consumption, and minimizing the silicon area. The second topic is the design and implementation of switching voltage regulators and their controllers, to provide a low-cost, compact, high efficient and reliable power conversion for integrated circuits. The first part of this dissertation includes a short, although deep, analysis on class D amplifiers, their history, principles of operation, architectures, performance metrics, practical design considerations, and their present and future market distribution. Moreover, the harmonic distortion of open-loop class D amplifiers based on pulse-width modulation (PWM) is analyzed by applying the duty cycle variation technique for the most popular carrier waveforms giving an easy and practical analytic method to evaluate the class D amplifier distortion and determine its specifications for a given linearity requirement. Additionally, three class D amplifiers, with an architecture based on sliding mode control, are proposed, designed, fabricated and tested. The amplifiers make use of a hysteretic controller to avoid the need of complex overhead circuitry typically needed in other architectures to compensate non-idealities of practical implementations. The design of the amplifiers based on this technique is compact, small, reliable, and provides a performance comparable to the state-of-the-art class D amplifiers, but consumes only one tenth of quiescent power. This characteristic gives to the proposed amplifiers an advantage for applications with minimal power consumption and very high performance requirements. The second part of this dissertation presents the design, implementation, and testing of switching voltage regulators. It starts with a description and brief analysis on the power converters architectures. It outlines the advantages and drawbacks of the main topologies, discusses practical design considerations, and compares their current and future market distribution. Then, two different buck converters are proposed to overcome the most critical issue in switching voltage regulators: to provide a stable voltage supply for electronic devices, with good regulation voltage, high efficiency performance, and, most important, a minimum number of components. The first buck converter, which has been designed, fabricated and tested, is an integrated dual-output voltage regulator based on sliding mode control that provides a power efficiency comparable to the conventional solutions, but potentially saves silicon area and input filter components. The design is based on the idea of stacking traditional buck converters to provide multiple output voltages with the minimum number of switches. Finally, a fully integrated buck converter based on sliding mode control is proposed. The architecture integrates the external passive components to deliver a complete monolithic solution with minimal silicon area. The buck converter employs a poly-phase structure to minimize the output current ripple and a hysteretic controller to avoid the generation of an additional high frequency carrier waveform needed in conventional solutions. The simulated results are comparable to the state-of-the-art works even with no additional post-fabrication process to improve the converter performance