Determining the device width to length ratios has typically been an iterative process for the custom IC digital design engineer. After the logic design phase is complete for a particular circuit, the designer would make an educated guess at the device sizes. Then by trial and error, using SPICE or another circuit simulator, suitable sizes would be determined. Unfortunately, this approach is time consuming and the resulting sizes are often a good bit larger than they need to be to maintain a certain speed because of the lack of a rigorous sizing methodology. This paper describes a method for reducing the time in obtaining a CMOS circuit design by providing the designer with transistor sizes which yield consistent gate to gate propagation delays within a delay path. The technical justifications are developed and several test cases are synthesized to illustrate this method. Switching time accuracy is verified using SPICE and the automatically generated sizes. A program written in the Ada language to perform device sizing is discussed as well.
The ramifications of area reduction are discussed as it pertains to custom and semicustom design methodologies. Algorithms to perform area minimization are presented along with other enhancements to the program
