TiN/HfO2/SiO2/Si gate stacks reliability : Contribution of HfO2 and interfacial SiO2 layer

Hafnium Oxide based gate stacks are considered to be the potential candidates to replace SiO2 in complementary metal-oxide-semiconductor (CMOS), as they reduce the gate leakage by over 100 times while keeping the device performance intact. Even though considerable performance improvement has been achieved, reliability of high-κ devices for the next generation of transistors (45nm and beyond) which has an interfacial layer (IL: typically SiO2) between high-κ and the substrate, needs to be investigated. To understand the breakdown mechanism of high-κ/SiO2 gate stack completely, it is important to study this multi-layer structure extensively. For example, (i) the role of SiO2 interfacial layers and bulk high-κ gate dielectrics without any interfacial layer can be investigated separately while maintaining same growth conditions; (ii) the evolution of breakdown process can be studied through stress induced leakage current (SILC); (iii) relationship of various degradation mechanisms such as negative bias temperature instability (NBTI) with that of the dielectric breakdown; and (iv) a fast evaluation process to estimate statistical breakdown distribution. In this dissertation a comparative study was conducted to investigate individual breakdown characteristics of high-κ/IL (ISSG SiO2)/metal gate stacks, in-situ steam generated (ISSG)-SiO2 MOS structures and HfO2-only metal-insulator-metal (MIM) capacitors. Experimental results indicate that after constant voltage stress (CVS) identical degradation for progressive breakdown and SILC were observed in high-κ/IL and SiO2-only MOS devices, but HfO2-only MIM capacitors showed insignificant SILC and progressive breakdown until it went into hard breakdown. Based on the observed SILC behavior and charge-to-breakdown (QBD), it was inferred that interfacial layer initiates progressive breakdown of metal gate/high-κ gate stacks at room temperature. From normalized SILC (ΔJg/Jg0) at accelerated temperature and activation energy of the timeto- breakdown (TBD), it was observed that IL initiates the gate stack breakdown at higher temperatures as well. A quantitative agreement was observed for key parameters of NBTI and time dependent dielectric breakdown (TDDB) such as the activation energies of threshold voltage change and SILC. The quality and thickness variation of the IL causes similar degradation on both NBTI and TDDB indicating that mechanism of these two reliability issues are related due to creation of identical defect types in the IL. CVS was used to investigate the statistical distribution of TBD, defined as soft or first breakdown where small sample size was considered. As TBD followed Weibull distribution, large sample size was not required. Since the failure process in static random access memory (SRAM) is typically predicted by the realistic TDDB model based on gate leakage current (IFAIL) rather than the conventional first breakdown criterion, the relevant failure distributions at IFAIL are non-Weibull including the progressive breakdown (PBD) phase for high-κ/metal gate dielectrics. A new methodology using hybrid two-stage stresses has been developed to study progressive breakdown phase further for high-κ and SiO2. It is demonstrated that VRS can be used effectively for quantitative reliability studies of progressive breakdown phase and final breakdown of high-κ and other dielectric materials; thus it can replace the time-consuming CVS measurements as an efficient methodology and reduce the resources manufacturing cost

Doctor of Philosophy

dissertationMicroelectromechanical systems (MEMS) resonators on Si have the potential to replace the discrete passive components in a power converter. The main intention of this dissertation is to present a ring-shaped aluminum nitride (AlN) piezoelectric microreson

Defect Induced Aging and Breakdown in High-k Dielectrics

abstract: High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use. In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Silicon Nitride Deposition, Chromium Corrosion Mechanisms and Source/Drain Parasitic Resistance in Amorphous Silicon Thin Film transistors

Hydrogenated amorphous silicon (a-Si:H) based thin film transistors (TFTs) are finding increased application as switching elements in active-matrix liquid crystal displays (AMLCDs). Extensive research has been focussed on optimizing fabrication conditions to improve materials quality and on reducing channel length to increase device speed. However, the basic physics and chemistry have not yet been fully understood. In addition, little attention has been paid to the significant effect of source/drain parasitics. The work described in this thesis is closely related to the speed and stability issues on the discrete device level. Specifically, the influence of gate nitride deposition and its NH3 plasma treatment has been studied. The competing effects of nitridation reaction and radiation damage were found to cause an interesting trade-off between the device stability and speed. Further effort was devoted to the analysis of an important TFT failure phenomenon. Both electrical and spectroscopic techniques were utilized for gate Cr corrosion studies. It was determined that the corrosion was largely promoted by the CF4 plasma exposure of Cr during the fabrication. Finally, new test structures were designed, fabricated and characterized to study the source/drain parasitic resistance

Novel techniques for the design and practical realization of switched-capacitor circuits in deep-submicron CMOS technologies

Dissertação apresentada para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores pela Universidade Nova de Lisboa, Faculdade de Ciências e TecnologiaSwitches presenting high linearity are more and more required in switched-capacitor circuits,namely in 12 to 16 bits resolution analog-to-digital converters. The CMOS technology evolves continuously towards lower supply voltages and, simultaneously, new design techniques are necessary to fulfill the realization of switches exhibiting a high dynamic range and a distortion compatible with referred resolutions. Moreover, with the continuously downing of the sizes, the physic constraints of the technology must be considered to avoid the excessive stress of the devices when relatively high voltages are applied to the gates. New switch-linearization techniques, with high reliability, must be necessarily developed and demonstrated in CMOS integrated circuits. Also, the research of new structures of circuits with switched-capacitor is permanent. Simplified and efficient structures are mandatory, adequate to the new demands emerging from the proliferation of portable equipments, necessarily with low energy consumption while assuring high performance and multiple functions. The work reported in this Thesis comprises these two areas. The behavior of the switches under these new constraints is analyzed, being a new and original solution proposed, in order to maintain the performance. Also, proposals for the application of simpler clock and control schemes are presented, and for the use of open-loop structures and amplifiers with localfeedback. The results, obtained in laboratory or by simulation, assess the feasibility of the presented proposals

A 0.18µm CMOS UWB wireless transceiver for medical sensing applications

Recently, there is a new trend of demand of a biomedical device that can continuously monitor patient’s vital life index such as heart rate variability (HRV) and respiration rate. This desired device would be compact, wearable, wireless, networkable and low-power to enable proactive home monitoring of vital signs. This device should have a radar sensor portion and a wireless communication link all integrated in one small set. The promising technology that can satisfy these requirements is the impulse radio based Ultra-wideband (IR-UWB) technology. Since Federal Communications Commission (FCC) released the 3.1GHz-10.6GHz frequency band for UWB applications in 2002 [1], IR-UWB has received significant attention for applications in target positioning and wireless communications. IR-UWB employs extremely narrow Gaussian monocycle pulses or any other forms of short RF pulses to represent information. In this project, an integrated wireless UWB transceiver for the 3.1GHz-10.6GHz IR-UWB medical sensor was developed in the 0.18µm CMOS technology. This UWB transceiver can be employed for both radar sensing and communication purposes. The transceiver applies the On-Off Keying (OOK) modulation scheme to transmit short Gaussian pulse signals. The transmitter output power level is adjustable. The fully integrated UWB transceiver occupies a core area of 0.752mm^2 and the total die area of 1.274mm^2 with the pad ring inserted. The transceiver was simulated with overall power consumption of 40mW for radar sensing. The receiver is very sensitive to weak signals with a sensitivity of -73.01dBm. The average power of a single pulse is 9.8µW. The pulses are not posing any harm to human tissues. The sensing resolution and the target positioning precision are presumably sufficient for heart movement detection purpose in medical applications. This transceiver can also be used for high speed wireless data communications. The data transmission rate of 200 Mbps was achieved with an overall power consumption of 57mW. A combination of sensing and communications can be used to build a low power sensor

Fabrication and nano-scale characterisation of ferroelectric thin films

PhD ThesisThis thesis focuses on the fabrication and characterisation of BaTiO3 thin films. One of the aims is to deposit amorphous BaTiO3 films on conductive thin films through sputtering at temperatures compatible with semiconductor manufacturing, followed by post deposition annealing to crystallise these films. However, rapid thermal processing (RTP) is known to create pinholes and cracks due to thermal mismatches between the electrode and insulator, causing degradation of the film quality. Initial focus was to develop thin film electrodes which can withstand process temperatures above 800 C. Deposition conditions, including the nitrogen flow rate relative to that of argon during deposition were optimised to obtain TiNx with least resistivity and excellent material properties through reactive sputtering. TiNx films deposited at various nitrogen flow rates were then annealed in a non-oxidising condition and their properties were thoroughly studied. Films deposited at the highest nitrogen flow rate (95%) showed least variation in resistivity and showed excellent material properties even after a high temperature anneal. BaTiO3 films of varying thicknesses were deposited on TiNx using RF-sputtering and subjected to RTP at various temperatures. It was found that there exists a critical thickness for each RTP temperature below which BaTiO3 films are pinhole free. A process was then developed by depositing and annealing multiple layers of BaTiO3 films, with the thickness of each deposition less than the critical thickness. It was observed that the multi-layered films are stable and pinhole free with a smooth surface while the single layers of equivalent thicknesses showed cracked surfaces. Current-atomic force microscopy studies showed leakage current through large pinholes in single-layered films, whereas the pinholes were not the leakage path for multi-layered films. Metal-insulator-metal capacitor structures were also fabricated using BaTiO3 with TiNx top and bottom electrodes and the fringing effects in leakage characteristics were studied. Finally, the polarisation reversal mechanism in BaTiO3 was investigated using piezoresponse force spectroscopy (PFS). It was experimentally demonstrated that the polarisation reversal in these materials is a two-step process, which involves polarisation rotation and switching when the applied electric field is not parallel to the crystallographic orientation of the grain. However, it is a single step switching when the polarisation and the electric field are parallel, as widely perceived. The two step polarisation reversal was found to help [101] and [111] oriented grains to switch at a lower electric field compared to [001] grains.Engineering and Physical Sciences Research Council (EPSRC), UK: Intel Ireland

Development of 20 GHz monolithic transmit modules

The history of the development of a transmit module for the band 17.7 to 20.2 GHz is presented. The module was to monolithically combine, on one chip, five bits of phase shift, a buffer amplifier and a power amplifier to produce 200 mW to the antenna element. The approach taken was MESFET ion implanted device technology. A common pinch-off voltage was decided upon for each application. The beginning of the total integration phases revealed hitherto unencountered hazards of large microwave circuit integration which were successfully overcome. Yield and customer considerations finally led to two separate chips, one containing the power amplifiers and the other containing the complete five bit phase shifter

Design for reliability applied to RF-MEMS devices and circuits issued from different TRL environments

Ces travaux de thèse visent à aborder la fiabilité des composants RF-MEMS (commutateurs en particulier) pendant la phase de conception en utilisant différents approches de procédés de fabrication. Ça veut dire que l'intérêt est focalisé en comment éliminer ou diminuer pendant la conception les effets des mécanismes de défaillance plus importants au lieu d'étudier la physique des mécanismes. La détection des différents mécanismes de défaillance est analysée en utilisant les performances RF du dispositif et le développement d'un circuit équivalent. Cette nouvelle approche permet à l'utilisateur final savoir comment les performances vont évoluer pendant le cycle de vie. La classification des procédés de fabrication a été faite en utilisant le Technology Readiness Level du procédé qui évalue le niveau de maturité de la technologie. L'analyse de différentes approches de R&D est décrite en mettant l'accent sur les différences entre les niveaux dans la classification TRL. Cette thèse montre quelle est la stratégie optimale pour aborder la fiabilité en démarrant avec un procédé très flexible (LAAS-CNRS comme exemple de baisse TRL), en continuant avec une approche composant (CEA-Leti comme moyenne TRL) et en finissant avec un procédé standard co-intégré CMOS-MEMS (IHP comme haute TRL) dont les modifications sont impossibles.This thesis is intended to deal with reliability of RF-MEMS devices (switches, in particular) from a designer point of view using different fabrication process approaches. This means that the focus will be on how to eliminate or alleviate at the design stage the effects of the most relevant failure mechanisms in each case rather than studying the underlying physics of failure. The detection of the different failure mechanisms are investigated using the RF performance of the device and the developed equivalent circuits. This novel approach allows the end-user to infer the evolution of the device performance versus time going one step further in the Design for Reliability in RF-MEMS. The division of the fabrication process has been done using the Technology Readiness Level of the process. It assesses the maturity of the technology prior to incorporating it into a system or subsystem. An analysis of the different R&D approaches will be presented by highlighting the differences between the different levels in the TRL classification. This thesis pretend to show how reliability can be improved regarding the approach of the fabrication process starting from a very flexible one (LAAS-CNRS as example of low-TRL) passing through a component approach (CEA-Leti as example of medium-TRL) and finishing with a standard co-integrated CMOS-MEMS process (IHP example of high TRL)

Intra-level dielectric reliability in deep sub-micron copper interconnects

Master'sMASTER OF ENGINEERIN