Design Methologies for Integrated Inductor-Based Soft-Switching DC DC Converters

This paper presents a study on resonant converter topologies targeted for CMOS integration. Design methodologies to optimize efficiency for the integration of Quasi-Resonant and Quasi-Square-Wave converters are proposed. A power loss model is used to optimize the design parameters of the power stage, including the driver circuits, and also to conclude about CMOS technology limitations. Based on this discussion, and taking as reference a 0.35μm CMOS process, two converters are designed to validate the proposal: a Quasi Resonant boost converter operating at 100MHz and a Quasi-Square-Wave buck converter operating at 70MHz. Simulation results confirm the feasibility of these topologies for monolithic integration

Optimization of DC-DC Converters via Geometric Programming

The paper presents a new methodology for optimizing the design of DC-DC converters. The magnitudes that we take into account are efficiency, ripples, bandwidth, and RHP zero placement. We apply a geometric programming approach, because the variables are positives and the constraints can be expressed in a posynomial form. This approach has all the advantages of convex optimization. We apply the proposed methodology to a boost converter. The paper also describes the optimum designs of a buck converter and a synchronous buck converter, and the method can be easily extended to other converters. The last example allows us to compare the efficiency and bandwidth between these optimal-designed topologies

Highly Integrated Dc-dc Converters

A monolithically integrated smart rectifier has been presented first in this work. The smart rectifier, which integrates a power MOSFET, gate driver and control circuitry, operates in a self-synchronized fashion based on its drain-source voltage, and does not need external control input. The analysis, simulation, and design considerations are described in detail. A 5V, 5-µm CMOS process was used to fabricate the prototype. Experimental results show that the proposed rectifier functions as expected in the design. Since no dead-time control needs to be used to switch the sync-FET and ctrl-FET, it is expected that the body diode losses can be reduced substantially, compared to the conventional synchronous rectifier. The proposed self-synchronized rectifier (SSR) can be operated at high frequencies and maintains high efficiency over a wide load range. As an example of the smart rectifier\u27s application in isolated DC-DC converter, a synchronous flyback converter with SSR is analyzed, designed and tested. Experimental results show that the operating frequency could be as high as 4MHz and the efficiency could be improved by more than 10% compared to that when a hyper fast diode rectifier is used. Based on a new current-source gate driver scheme, an integrated gate driver for buck converter is also developed in this work by using a 0.35µm CMOS process with optional high voltage (50V) power MOSFET. The integrated gate driver consists both the current-source driver for high-side power MOSFET and low-power driver for low-side power iv MOSFET. Compared with the conventional gate driver circuit, the current-source gate driver can recovery some gate charging energy and reduce switching loss. So the current-source driver (CSD) can be used to improve the efficiency performance in high frequency power converters. This work also presents a new implementation of a power supply in package (PSiP) 5MHz buck converter, which is different from all the prior-of-art PSiP solutions by using a high-Q bondwire inductor. The high-Q bondwire inductor can be manufactured by applying ferrite epoxy to the common bondwire during standard IC packaging process, so the new implementation of PSiP is expected to be a cost-effective way of power supply integration

Development of Efficient Soft Switching Synchronous Buck Converter Topologies for Low Voltage High Current Applications

Switched mode power supplies (SMPS) have emerged as the popular candidate in all the power processing applications. The demand is soaring to design high power density converters. For reducing the size, weight, it is imperative to channelize the power at high switching frequency. High switching frequency converters insist upon soft switching techniques to curtail the switching losses. Several soft switching topologies have been evolved in the recent years. Nowadays, the soft switching converters are vastly applied modules and the demand is increasing for high power density and high efficiency modules by minimizing the conduction and switching losses. These modules are generally observed in many applications such as laptops, desktop processors for the enhancement of the battery life time. Apart from these applications, solar and spacecraft applications demand is increasing progressively for stressless and more efficient modules for maximizing the storage capacity which inturn enhances the power density that improves the battery life to supply in the uneven times. Modern trends in the consumer electronic market focus increases in the demand of lower voltage supplies. Conduction losses are significantly reduced by synchronous rectifiers i.e., MOSFET’s are essentially used in many of the low voltage power supplies. Active and passive auxiliary circuits are used in tandem with synchronous rectifier to diminish the crucial loss i.e., switching loss and also it minimizes the voltage and current stresses of the semiconductor devices. The rapid progress in the technology and emerging portable applications poses serious challenges to power supply design engineers for an efficient power converter design at high power density. The primary aim is to design and develop high efficiency, high power density topologies like: buck, synchronous buck and multiphase buck converters with the integration of soft switching techniques to minimize conduction and switching losses sustaining the voltage and current stresses within the tolerable range. In this work, two ZVT-ZCT PWM synchronous buck converters are introduced, one with active auxiliary circuit and the other one with passive auxiliary circuit. The operating principle and comprehensive steady state analysis of the ZVT-ZCT PWM synchronous buck converters are presented. The converters are designed to have high efficiency and low voltage that is suitable for high power density application. The semiconductor devices used in the topologies in addition to the main switch operate with soft switching conditions. The viii Abstract topologies proposed render a large overall efficiency in contrast to the contemporary topologies. In addition the circuit’s size is less, reliable and have high performance-cost ratio. The new generation microprocessor demands the features such as low voltage, high current, high power density and high efficiency etc., in the design of power supplies. The supply voltage for the future generation microprocessors must be low, in order to decrease the power consumption. The voltage levels are dripping to a level even less than 0.7V, and the power consumption increases as there is an increase in the current requirement for the processor. In order to meet the demands of the new generation microprocessor power supply, a soft switching multiphase PWM synchronous buck converter is proposed. The losses in the proposed topology due to increasing components are pared down by the proposed soft switching technique. The proposed converters in this research work are precisely described by the mathematical modelling and their operational modes. The practicality of the proposed converters for different applications is authenticated by their simulation and experimental results

Low-voltage-swing Monolithic DC-DC Conversion

Abstract—A low-voltage-swing MOSFET gate drive technique is proposed in this paper for enhancing the efficiency characteristics of high-frequency-switching dc–dc converters. The parasitic power dissipation of a dc–dc converter is reduced by lowering the voltage swing of the power transistor gate drivers. A comprehensive circuit model of the parasitic impedances of a monolithic buck converter is presented. Closed-form expressions for the total power dissipation of a low-swing buck converter are proposed. The effect of reducing the MOSFET gate voltage swings is explored with the proposed circuit model. A range of design parameters is evaluated, permitting the development of a design space for full integration of active and passive devices of a low-swing buck converter on the same die, for a target CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is lower than a standard full voltage swing. An efficiency of 88 % at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 to 0.9 V with a low-swing dc–dc converter based on a 0.18- m CMOS technology. The power dissipation of a low-swing dc–dc converter is reduced by 27.9 % as compared to a standard full-swing dc–dc converter. Index Terms—Buck converter, dc–dc converters, enhanced efficiency, high frequency, low power, low swing, monolithic integration, on-chip voltage conversion, parameter optimization, parasitic impedances, power dissipation modeling, power supply, reduced energy dissipation, reduced voltage swing, switching voltage regulator. I

A Dual-Supply Buck Converter with Improved Light-Load Efficiency

Power consumption and device size have been placed at the primary concerns for battery-operated portable applications. Switching converters gain popularity in powering portable devices due to their high efficiency, compact sizes and high current delivery capability. However portable devices usually operate at light loads most of the time and are only required to deliver high current in very short periods, while conventional buck converter suffers from low efficiency at light load due to the switching losses that do not scale with load current. In this research, a novel technique for buck converter is proposed to reduce the switching loss by reducing the effective voltage supply at light load. This buck converter, implemented in TSMC 0.18 micrometers CMOS technology, operates with a input voltage of 3.3V and generates an output voltage of 0.9V, delivers a load current from 1mA to 400mA, and achieves 54 percent ~ 91 percent power efficiency. It is designed to work with a constant switching frequency of 3MHz. Without sacrificing output frequency spectrum or output ripple, an efficiency improvement of up to 20 percent is obtained at light load

Hybrid monolithic integration of high-power DC-DC converters in a high-voltage technology

The supply of electrical energy to home, commercial, and industrial users has become ubiquitous, and it is hard to imagine a world without the facilities provided by electrical energy. Despite the ever increasing efficiency of nearly every electrical application, the worldwide demand for electrical power continues to increase, since the number of users and applications more than compensates for these technological improvements. In order to maintain the affordability and feasibility of the total production, it is essential for the distribution of the produced electrical energy to be as efficient as possible. In other words the loss in the power distribution is to be minimized. By transporting electrical energy at the maximum safe voltage, the current in the conductors, and the associated conduction loss can remain as low as possible. In order to optimize the total efficiency, the high transportation voltage needs to be converted to the appropriate lower voltage as close as possible to the end user. Obviously, this conversion also needs to be as efficient, affordable, and compact as possible. Because of the ever increasing integration of electronic systems, where more and more functionality is combined in monolithically integrated circuits, the cost, the power consumption, and the size of these electronic systems can be greatly reduced. This thorough integration is not limited to the electronic systems that are the end users of the electrical energy, but can also be applied to the power conversion itself. In most modern applications, the voltage conversion is implemented as a switching DC-DC converter, in which electrical energy is temporarily stored in reactive elements, i.e. inductors or capacitors. High switching speeds are used to allow for a compact and efficient implementation. For low power levels, typically below 1 Watt, it is possible to monolithically implement the voltage conversion on an integrated circuit. In some cases, this is even done on the same integrated circuit that is the end user of the electrical energy to minimize the system dimensions. For higher power levels, it is no longer feasible to achieve the desired efficiency with monolithically integrated components, and some external components prove indispensable. Usually, the reactive components are the main limiting factor, and are the first components to be moved away from the integrated circuit for increasing power levels. The semiconductor components, including the power transistors, remain part of the integrated circuit. Using this hybrid approach, it is possible in modern converterapplications to process around 60 Watt, albeit limited to voltages of a few Volt. For hybrid integrated converters with an output voltage of tens of Volt, the power is limited to approximately 10 Watt. For even higher power levels, the integrated power transistors also become a limiting factor, and are replaced with discrete power devices. In these discrete converters, greatly increased power levels become possible, although the system size rapidly increases. In this work, the limits of the hybrid approach are explored when using so-called smart-power technologies. Smart-power technologies are standard lowcost submicron CMOS technologies that are complemented with a number of integrated high-voltage devices. By using an appropriate combination of smart-power technologies and circuit topologies, it is possible to improve on the current state-of-the-art converters, by optimizing the size, the cost, and the efficiency. To determine the limits of smart-power DC-DC converters, we first discuss the major contributing factors for an efficient energy distribution, and take a look at the role of voltage conversion in the energy distribution. Considering the limitations of the technologies and the potential application areas, we define two test-cases in the telecommunications sector for which we want to optimize the hybrid monolithic integration in a smart-power technology. Subsequently, we explore the specifications of an ideal converter, and the relevant properties of the affordable smart-power technologies for the implementation of DC-DC converters. Taking into account the limitations of these technologies, we define a cost function that allows to systematically evaluate the different potential converter topologies, without having to perform a full design cycle for each topology. From this cost function, we notice that the de facto default topology selection in discrete converters, which is typically based on output power, is not optimal for converters with integrated power transistors. Based on the cost function and the boundary conditions of our test-cases, we determine the optimal topology for a smart-power implementation of these applications. Then, we take another step towards the real world and evaluate the influence of parasitic elements in a smart-power implementation of switching converters. It is noticed that the voltage overshoot caused by the transformer secondary side leakage inductance is a major roadblock for an efficient implementation. Since the usual approach to this voltage overshoot in discrete converters is not applicable in smart-power converters due to technological limitations, an alternative approach is shown and implemented. The energy from the voltage overshoot is absorbed and transferred to the output of the converter. This allows for a significant reduction in the voltage overshoot, while maintaining a high efficiency, leading to an efficient, compact, and low-cost implementation. The effectiveness of this approach was tested and demonstrated in both a version using a commercially available integrated circuit, and our own implementation in a smart-power integrated circuit. Finally, we also take a look at the optimization of switching converters over the load range by exploiting the capabilities of highly integrated converters. Although the maximum output power remains one of the defining characteristics of converters, it has been shown that most converters spend a majority of their lifetime delivering significantly lower output power. Therefore, it is also desirable to optimize the efficiency of the converter at reduced output current and output power. By splitting the power transistors in multiple independent segments, which are turned on or off in function of the current, the efficiency at low currents can be significantly improved, without introducing undesirable frequency components in the output voltage, and without harming the efficiency at higher currents. These properties allow a near universal application of the optimization technique in hybrid monolithic DC-DC converter applications, without significant impact on the complexity and the cost of the system. This approach for the optimization of switching converters over the load range was demonstrated using a boost converter with discrete power transistors. The demonstration of our smart-power implementation was limited to simulations due to an issue with a digital control block. On a finishing note, we formulate the general conclusions and provide an outlook on potential future work based on this research

Development of Improved Performance Switchmode Converters for Critical Load Applications

Emerging portable applications and the rapid advancement of technology have posed rigorous challenges to power engineers for an efficient power delivery at high power density. The foremost objectives are to develop high efficiency, high power density topologies such as: buck, synchronous buck and multiphase buck converters, with the implementation of soft switching technology to reduce switching losses maintaining voltage and current stresses within the permissible range. Demand of low voltage power supply for telecom system leads to narrow duty cycle which compels to increase operating switching frequency. Design of conventional buck converter under narrow duty cycle is quite objectionable since it leads to poor utilization of components as well as it degrades the system efficiency. A high switching frequency operation reduces the switch conduction time that leads to large increase in switching losses and increases the control complexity. Therefore, duty cycle has to be extended and at the same time switching losses have to be minimized. Transformer based topology can be used to extend the duty cycle. But to reduce switching losses soft switching techniques should be implemented. An isolated buck converter with simple clamp capacitor scheme is proposed to reduce switching losses and to extend duty cycle by optimizing the turn ratio. Extended duty cycle impose limit on dead time. Dead time has to be controlled with respect to duty cycle to reduce body diode conduction loss and to avoid the shoot through conditions in our proposed topology. The proposed clamp capacitor scheme control the dead time as well as provide better efficiency with reduction in switching losses maintaining ripples within the allowable range

Optimización del diseño de convertidores de potencia CC-CC

L'electrònica ha experimentat una gran evolució durant les últimes dècades. El número de dispositius i aplicacions electrònics ha augmentat exponencialment fins a convertir-se en elements indispensables de la nostra vida quotidiana. Concretament, en el campo de l’electrònica de potencia, els convertidores commutats CC-CC, àmpliament utilitzats en els sistemes d’alimentació d’ equips electrònics, requereixen d’una eficiència elevada. Així, en la tesis es presenta un nou mètode per al disseny de convertidors CC-CC que optimitza una funció objectiu no lineal amb restriccions no lineals. El model desenvolupat aborda, en la majoria dels casos, un problema que consisteix en el disseny òptim de mínimes pèrdues, es a dir, màxima eficiència. A pesar d’això, també es presenta, a mode d’exemple, el disseny òptim de convertidors maximitzant l’ample de banda. Es pretén mostrar així la facilitat amb que pot ser modificat el programa de disseny. El problema ha estat modelat com un programa de Programació Geomètrica per aprofitar les avantatges que ofereix l’optimització convexa.L'electrònica ha experimentat una gran evolució durant les últimes dècades. El número de dispositius i aplicacions electrònics ha augmentat exponencialment fins a convertir-se en elements indispensables de la nostra vida quotidiana. Concretament, en el campo de l’electrònica de potencia, els convertidores commutats CC-CC, àmpliament utilitzats en els sistemes d’alimentació d’ equips electrònics, requereixen d’una eficiència elevada. Així, en la tesis es presenta un nou mètode per al disseny de convertidors CC-CC que optimitza una funció objectiu no lineal amb restriccions no lineals. El model desenvolupat aborda, en la majoria dels casos, un problema que consisteix en el disseny òptim de mínimes pèrdues, es a dir, màxima eficiència. A pesar d’això, també es presenta, a mode d’exemple, el disseny òptim de convertidors maximitzant l’ample de banda. Es pretén mostrar així la facilitat amb que pot ser modificat el programa de disseny. El problema ha estat modelat com un programa de Programació Geomètrica per aprofitar les avantatges que ofereix l’optimització convexa.La electrónica ha experimentado una gran evolución en las últimas décadas. El número de dispositivos y aplicaciones electrónicas ha aumentado exponencialmente hasta convertirse en elementos indispensables en nuestra vida cotidiana. Concretamente, en el campo de la electrónica de potencia, los convertidores conmutados CC-CC, ampliamente utilizados en los sistemas de alimentación de equipos electrónicos, requieren de una eficiencia elevada. Así, en la tesis se presenta un nuevo método para el diseño de convertidores CC-CC que optimiza una función objetivo no lineal con restricciones no lineales. El modelo desarrollado aborda, en la mayoría de los casos, un problema que consiste en el diseño óptimo de mínimas pérdidas, es decir, máxima eficiencia. Sin embargo, también se presenta, a modo de ejemplo, el diseño óptimo de convertidores maximizando el ancho de banda. Se pretende mostrar así la facilidad con que puede ser modificado el programa de diseño. El problema ha sido modelado como un programa de Programación Geométrica para aprovechar las ventajas que ofrece la optimización convexa.The electronics has evolved greatly in recent decades. The number of electronic devices and applications has grown exponentially to become indispensable in our daily lives. Specifically, in the field of power electronics, the power converters DC-DC, widely used in supply systems of electronic equipment, require a high efficiency. Thus, the thesis presents a new method for the design of DC-DC converters to optimize nonlinear objective function with nonlinear constraints. The model developed presented, in most cases, a problem which consists in the optimum design of minimum losses. However, also presents the optimal design of converters maximizing bandwidth. And is intended to show how easy it can be modified the design program. The problem is modelled as a Geometric Programming problem to exploit the advantages of convex optimization