A Novel Carbon Nanotube Field Effect Transistor based Arithmetic Computing Circuit for Low-power Analog Signal Processing Application

AbstractThere is a need to explore circuit application in new emerging technologies for their rapid commercialization as the CMOS technology is approaching its limits. Carbon Nanotube Field-Effect Transistor (CNFET) is a promising candidate for future electronic devices for low-power low-voltage digital or analog circuit application. In this paper, we presented a low-power, low- voltage CNFET operational amplifier (OPAMP) based analog arithmetic computing circuit such as inverting amplifier, non- inverting amplifier, summer, substractor, differentiator, and integrator for low-power analog signal processing application. The proposed computing circuits operation are studied by using HSPICE software for circuit simulation at 0.9V input supply voltage. Simulation results show that the proposed computing circuits well suited for low-power low-voltage analog signal processing application for their lower power consumption, and high speed operation

Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 µm CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Low-Power and Programmable Analog Circuitry for Wireless Sensors

Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits

Ultra-Low-Power Configurable Analog Signal Processor for Wireless Sensors

The demand for on-chip low-power Complementary Metal Oxide Semiconductor (CMOS) analog signal processing has significantly increased in recent years. Digital signal processors continue to shrink in size as transistors half in size every two years. However, digital signal processors (DSP\u27s) notoriously use more power than analog signal processors (APS\u27s). This thesis presents a configurable analog signal processor (CASP) used for wireless sensors. This CASP contains a multitude of processing blocks include the following: low pass filter (LPF), high pass filter (HPF) integrator, differentiator, operational transconductance amplifier (OTA), rectifier with absolute value functionality, and multiplier. Each block uses current-mode processing and operates in the sub-threshold region of operation. Current-mode processing allows for noise reduction, lower power consumption, and better dynamic range. Each block contains configurable current sources and capacitor banks for maximum adaptability. The blocks were designed, simulated, and fabricated in Cadence using IBM\u27s 130nm CMOS process. The processing blocks were combined into a four by three array and connected using specially designed interconnect fabric. A test structure including the LPF, HPF, and multiplier was also constructed for characterization purposes. The main goals for this project are frequency compression and creating a non-linear energy operator for neural spike detection. The test results for the low-pass filter, integrator, and frequency divider reflected the simulated values. The other blocks didn\u27t perform as well as in simulation. The interconnect fabric ties all the blocks together and achieved maximum configurability with negligible attenuation. In simulation, frequency compression was achieved with 30u[micro]W of power from a 1V supply rail

First order sigma-delta modulator of an oversampling ADC design in CMOS using floating gate MOSFETS

We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth

Analog Signal Processing Elements for Energy-Constrained Platforms

Energy constrained processing poses a number of challenges that have resulted in tremendous innovations over the past decade. Shrinking supply voltages and limited clock speeds have placed an emphasis on processing efficiency over the raw throughput of a processor. One of the approaches to increase processing efficiency is to use parallel processing with slower, lower resolution processing elements. By utilizing this parallel approach, power consumption can be decreased while maintaining data throughput relative to other more power-hungry architectures.;This low resolution / parallel architecture has direct application in the analog as well as the digital domain. Indeed, research shows that as the resolution of a signal processor falls below a system-dependent threshold, it is almost always more efficient to preform the processing in the analog domain. These continuous-time circuits have long been used in the most energy-constrained applications, ranging from pacemakers and cochlear implants to wireless sensor motes designed to run autonomously for months in the field.;Most audio processing techniques utilize spectral decomposition as the first step of their algorithms, whether by a FFT/DFT in the digital domain or a bank of bandpass filters in the analog domain. The work presented here is designed to function within the parallel, array-based environment of a bank of bandpass filters. Work to improve the simulation of programmable analog storage elements (Floating-Gate transistors) in typical SPICE-based simulators is presented, along with a novel method of harnessing the unique properties of these Floating-Gate (FG) transistors to extend the linear range of a differential pair. These improvements in simulation and linearity are demonstrated in a Variable-Gain Amplfier (VGA) to compress large differential inputs into small single-ended outputs suitable for processing by other analog elements. Finally, a novel circuit composed of only six transistors is proposed to compute the continuous-time derivative of a signal within the sub-banded architecture of the bandpass filter bank

Power supply current [IPS] based testing of CMOS amplifier circuit with and without floating gate input transistors

This work presents a case study, which attempts to improve the fault diagnosis and testability of the power supply current based testing methodology applied to a typical two-stage CMOS operational amplifier and is extended to operational amplifier with floating gate input transistors*. The proposed test method takes the advantage of good fault coverage through the use of a simple power supply current measurement based test technique, which only needs an ac input stimulus at the input and no additional circuitry. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. In the present work, variations of ac ripple in the power supply current IPS, passing through VDD under the application of an ac input stimulus is measured to detect injected faults in the CMOS amplifier. The effect of parametric variation is taken into consideration by setting tolerance limit of ± 5% on the fault-free IPS value. The fault is identified if the power supply current, IPS falls outside the deviation given by the tolerance limit. This method presented can also be generalized to the test structures of other floating-gate MOS analog and mixed signal integrated circuits