A 180nm CMOS Capacitorless Low Drop-Out Regulator for Battery-operated System

This paper presents a fully-integrated 180nm CMOS low drop-out regulator based on a simple telescopic cascode-compensated amplifier driving a PMOS pass-device. It provides a high precision 1.8V output voltage for battery voltages from 3.6V to 1.93V up to a 50mA load current with only 22μA quiescent current

Low drop-out voltage regulator as a candidate topology for photovoltaic solar facilities

This article aims to present the design of a 4.5-V, 450-mA low drop-out (LDO) voltage linear regulator based on a two-stage cascoded operational transconductance amplifier (OTA) as error amplifier for photovoltaic solar DC-DC regulation. The aforementioned two-stage OTA is designed with cascoded current mirroring technique to boost up the output impedance. The proposed OTA has a DC gain of 101 dB under no load condition. The designed reference voltage included in the LDO regulator is provided by a band gap reference with the temperature coefficient (T¿) of 0.025 mV/ºC. The proposed LDO regulator has a maximum drop-out voltage of 0.5 V @ 450 mA of load current, and has the worst case power supply rejection ratio (PSRR) of [54.5 dB, 34.3 dB] @ [100 Hz, 10 kHz] in full load condition. All the proposed circuits are designed using a 0.35 µm CMOS technology. The design is checked in order to corroborate its performance for wide range of input voltage, founding that the circuit design works fine meeting all the initial specification requirements.Peer ReviewedPostprint (published version

Bipolar-CMOS-DMOS Process-Based a Robust and High-Accuracy Low Drop-Out Regulator

A 40V BCD process high-accuracy and robust Low Drop-Out Regulator was proposed and tape-out in CSMC; the LDO was integrated in a LED Control and Driver SOC of outdoor applications. The proposed LDO converted the 12V~40V input power to 5V for the low voltage circuits inside the SOC. The robustness of LDO was important because the application condition of the SOC was bad. It was simulated in all process corner, -55℃~150℃ temperature and 12V~40V power voltage conditions. Simulation result shows that the LDO works robustly in conditions mentioned above. The default precision of LDO output voltage is ±2.75% max in all conditions, moreover, by utilizing a trim circuit in the feedback network, the precision can be improved to ±0.5% max after being trimmed by 3 bit digital trim signal Trim[3:1]. The total size of the proposed LDO is 135um*450um and the maximum current consumption is 284uA

A Low-quiescent Current Full on-chip 1.2 V CMOS Low Drop-Out Regulator

This paper presents a fully-integrated low-power 0.18 µm CMOS Low-Dropout (LDO) regulator for battery operated portable devices. It provides an accurate 1.2 V output voltage from 3.3 V to 1.3 V input voltages up with only 5.9 µA quiescent current, including an all-MOS 0.4 V reference voltage

Design of Low Drop-Out Regulator with Low Voltage

随着工艺的发展及许多SOC产品及便携式电子产品的工作电压不断下降，省电观念越来越引人注目，对提供电源的芯片要求越来越高。针对供电电源日趋低压化，以及节能环保意识成为各个国家及众多消费者的共识，低电源电压下能工作且具有低功耗成为线性稳压器的发展趋势。本文提出了一种输出电压1.5V，输入电压可以低至1.7V的情况下稳定工作并能提供300mA电流的低压差线性稳压器电路，整个线性稳压器电路的静态电流低于40uA。与传统的低压差线性稳压器相比，本文设计的低压差线性稳压器电路系统提出了利用有源前馈米勒补偿（AFFC）与共源共栅米勒补偿相结合的新颖动态米勒补偿结构，这种补偿结构下的电路系统具有恒定的带宽（1...With the developments of electronics and telecommunication, portable electronical products become more and more popular. The developments of power management technologies and applications are rapidly promoted. A high-accuracy, micro power and low-dropout (LDO) voltage regulator is presented in this paper. A novel compensation structure that using the Active-Feedback Frequency Compensation (AFF...学位：工程硕士院系专业：信息科学与技术学院电子工程系_仪器仪表工程学号：X20043000

A New Design Methodology For Enhancing The Transient Loading Of Low Drop-out Regulators (LDRs)

A new simple design methodology which makes LDR output nearly insensitive to jumps of the load current for long times is proposed. This methodology is tested for more than 104 seconds. Our procedure leans on cross coupling of the time second derivative of the LDR power transistor gate and drain voltages along with their currents. This technique keeps low values of these currents in order of nano or hundreds of micro amperes for undershot or overshot cases, respectively. The introduced methodology has been applied to a standard CMOS of 0.18μm technology for NMOS transistors and validated using MATLAB R2014a

Current Feedback-Based High Load Current Low Drop-Out Voltage Regulator in 65-nm CMOS Technology

The motivation for this paper was to design a current feedback-based high load current, low drop-out (LDO) voltage regulator. A bandgap voltage reference (BGR) was also designed in conjunction with the LDO to simulate realistic environments. The schematic was designed with Cadence Virtuoso Schematic XL, using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS library, used for Internet of Things (IoT) System on Chip (SoC) applications. The proposed capacitor-less LDO with BGR provided an average temperature coefficient (TC) of 13.34 ppm/℃ within the range of -40 to 125 ℃. This was in accordance with military standards to gain a higher stability and power supply rejection ratio (PSRR). The proposed capacitor-less LDO also achieved a 200 mA load current with an error percentage of 0.246% and a -21.47 dB PSRR at 100 KHz with a current based structure. This thesis concluded with the application of capacitor-less LDO in medical IoT devices, followed by the future of medical device development