Hardwarearchitektur für einen universellen LDPC Decoder

Im vorliegenden Beitrag wird eine universelle Decoderarchitektur für einen Low-Density Parity-Check (LDPC) Code Decoder vorgestellt. Anders als bei den in der Literatur häufig beschriebenen Architekturen für strukturierte Codes ist die hier vorgestellte Architektur frei programmierbar, so dass jeder beliebige LDPC Code durch eine Änderung der Initialisierung des Speichers für die Prüfmatrix mit derselben Hardware decodiert werden kann. Die größte Herausforderung beim Entwurf von teilparallelen LDPC Decoder Architekturen liegt im konfliktfreien Datenaustausch zwischen mehreren parallelen Speichern und Berechnungseinheiten, wozu ein Mapping und Scheduling Algorithmus benötigt wird. Der hier vorgestellte Algorithmus stützt sich auf Graphentheorie und findet für jeden beliebigen LDPC Code eine für die Architektur optimale Lösung. Damit sind keine Wartezyklen notwendig und die Parallelität der Architektur wird zu jedem Zeitpunkt voll ausgenutzt

An LDPC Decoder Architecture for Wireless Sensor Network Applications

The pervasive use of wireless sensors in a growing spectrum of human activities reinforces the need for devices with low energy dissipation. In this work, coded communication between a couple of wireless sensor devices is considered as a method to reduce the dissipated energy per transmitted bit with respect to uncoded communication. Different Low Density Parity Check (LDPC) codes are considered to this purpose and post layout results are shown for a low-area low-energy decoder, which offers percentage energy savings with respect to the uncoded solution in the range of 40%–80%, depending on considered environment, distance and bit error rate

A Novel Conflict-Free Memory and Processor Architecture for DVB-T2 LDPC Decoding

In this paper, we present a flexible architecture for an LDPC decoder that fully exploits the structure of the codes defined in the DVB-T2 standard (Digital Video Broadcasting - Second Generation Terrestrial). We propose a processor and memory architecture which uses the flooding schedule and has no memory access conflicts, which are encountered in serial schedule decoders proposed in the literature. Thus, unlike previous works, we do not require any extra logic or ad hoc designs to resolve memory conflicts. Despite the typically slower convergence of flooding schedule compared to serial schedule decoders, our ar- chitecture meets the throughput and BER requirements specified in the DVB-T2 standard. Our design allows a trade-off between memory size and performance by the selection of the number of bits per message without affecting the general memory arrangement. Besides, our architecture is not algorithm specific: any check-node message processing algorithm can be used (Sum-Product, Min-Sum, etc.) without modifying the basic architecture. Furthermore, by simply adding relevant small ROM tables, we get a decoder that is fully compatible with all three second generation DVB standards (DVB-T2, DVB-S2 and DVB-C2). We present simulation results to demonstrate the viability of our solution both functionally and in terms of the bit-error rate performance. We also discuss the memory requirements and the throughput of the architecture, and present preliminary synthesis results in CMOS 130nm technology

Physical layer forward error correcetion in DVB-S2 networks.

Thesis (M.Sc.Eng.)-University of KwaZulu-Natal, Durban, 2012.The rapid growth of wireless systems has shown little sign of ceasing, due to increased consumer demand for reliable interactive services. A key component of the development has centered on satellite networks, which allows provision of services in scenarios where terrestrial systems are not viable. The Digital Video Broadcasting-Satellite Second Generation (DVB-S2) standard was developed for use in satellite broadcast applications, the foremost being video broadcasting. Inherent to DVB-S2 is a powerful forward error correction (FEC) module, present in both the Physical and Data Link Layer. Improving the error correcting capability of the FEC is a natural advent in improving the quality of service of the protocol. This is more crucial in real time satellite video broadcast where retransmission of data is not viable, due to high latency. The Physical Layer error correcting capability is implemented in the form of a concatenated BCH-LDPC code. The DVB-S2 standard does not define the decoding structure for the receiver system however many powerful decoding systems have been presented in the literature; the Belief Propagation-Chase concatenated decoder being chief amongst them. The decoder utilizes the concept of soft information transfer between the Chase and Belief Propagation (BP) decoders to provide improved error correcting capability above that of the component decoders. The following dissertation is motivated by the physical layer (PL) FEC scheme, focused on the concatenated Chase-BP decoder. The aim is to generate results based on the BP-Chase decoder in a satellite channel as well as improve the error correcting capability. The BP-Chase decoder has shown to be very powerful however the current literature provides performance results only in AWGN channels. The AWGN channel however is not an accurate representation of a land-mobile satellite (LMS) channel; it does not consider the effect of shadowing, which is prevalent in satellite systems. The development of Markov chain models have allowed for better description of the characteristics of the LMS channel. The outcome being the selection of a Ku band LMS channel model. The selected LMS channel model is composed of 3 states, each generating a different degree of shadowing. The PL system has been simulated using the LMS channel and BP-Chase receiver to provide a more accurate representation of performance of a DVB-S2 network. The effect of shadowing has shown to reduce coding performance by approximately 4dB, measured over several code lengths and decoders, when compared with AWGN performance results. The second body of work aims to improve the error correcting capability of the BP-Chase decoder, concentrating on improving the LDPC decoding module performance. The LDPC system is the basis for the powerful error correcting ability of the concatenated scheme. In attempting to improve the LDPC decoder a reciprocal improvement is expected in the overall decoding performance of the concatenated decoder. There have been several schemes presented which improve BP performance. The BP-Ordered statistics decoder (OSD) was selected through a process of literary review; a novel decoding structure is presented incorporating the BP-OSD decoder into the BP-Chase structure. The result of which is the BP-OSD-Chase decoder. The decoder contains two stages of concatenation; the first stage implements the BPOSD algorithm which decodes the LDPC code and the second stage decodes the BCH code using the Chase algorithm. Simulation results of the novel decoder implementation in the DVBS2 PL show a coding gain of 0.45dB and 0.15dB versus the BP and BP-Chase decoders respectively, across both the AWGN and LMS channel

Research on high performance LDPC decoder

制度:新 ; 報告番号:甲3272号 ; 学位の種類:博士(工学) ; 授与年月日:2011/3/15 ; 早大学位記番号:新557

New Algorithms for High-Throughput Decoding with Low-Density Parity-Check Codes using Fixed-Point SIMD Processors

Most digital signal processors contain one or more functional units with a single-instruction, multiple-data architecture that supports saturating fixed-point arithmetic with two or more options for the arithmetic precision. The processors designed for the highest performance contain many such functional units connected through an on-chip network. The selection of the arithmetic precision provides a trade-off between the task-level throughput and the quality of the output of many signal-processing algorithms, and utilization of the interconnection network during execution of the algorithm introduces a latency that can also limit the algorithm\u27s throughput. In this dissertation, we consider the turbo-decoding message-passing algorithm for iterative decoding of low-density parity-check codes and investigate its performance in parallel execution on a processor of interconnected functional units employing fast, low-precision fixed-point arithmetic. It is shown that the frequent occurrence of saturation when 8-bit signed arithmetic is used severely degrades the performance of the algorithm compared with decoding using higher-precision arithmetic. A technique of limiting the magnitude of certain intermediate variables of the algorithm, the extrinsic values, is proposed and shown to eliminate most occurrences of saturation, resulting in performance with 8-bit decoding nearly equal to that achieved with higher-precision decoding. We show that the interconnection latency can have a significant detrimental effect of the throughput of the turbo-decoding message-passing algorithm, which is illustrated for a type of high-performance digital signal processor known as a stream processor. Two alternatives to the standard schedule of message-passing and parity-check operations are proposed for the algorithm. Both alternatives markedly reduce the interconnection latency, and both result in substantially greater throughput than the standard schedule with no increase in the probability of error

Field-programmable gate-array (FPGA) implementation of low-density parity-check (LDPC) decoder in digital video broadcasting - second generation satellite (DVB-S2)

In recent years, LDPC codes are gaining a lot of attention among researchers. Its near-Shannon performance combined with its highly parallel architecture and lesser complexity compared to Turbo-codes has made LDPC codes one of the most popular forward error correction (FEC) codes in most of the recently ratified wireless communication standards. This thesis focuses on one of these standards, namely the DVB-S2 standard that was ratified in 2005. In this thesis, the design and architecture of a FPGA implementation of an LDPC decoder for the DVB-S2 standard are presented. The decoder architecture is an improvement over others that are published in the current literature. Novel algorithms are devised to use a memory mapping scheme that allows for 360 functional units (FUs) used in decoding to be implemented using the Sum-Product Algorithm (SPA). The functional units (FU) are optimized for reduced hardware resource utilization on a FPGA with a large number of configurable logic blocks (CLBs) and memory blocks. A novel design of a parity-check module (PCM) is presented that verifies the parity-check equations of the LDPC codes. Furthermore, a special characteristic of five of the codes defined in the DVB-S2 standard and their influence on the decoder design is discussed. Three versions of the LDPC decoder are implemented, namely the 360-FU decoder, the 180-FU decoder and the hybrid 360/180-FU decoder. The decoders are synthesized for two FPGAs. A Xilinx Virtex-II Pro family FPGA is used for comparison purposes and a Xilinx Virtex-6 family FPGA is used to demonstrate the portability of the design. The synthesis results show that the hardware resource utilization and minimum throughput of the decoders presented are competitive with a DVB-S2 LDPC decoder found in the current literature that also uses FPGA technology

Field-programmable gate-array (FPGA) implementation of low-density parity-check (LDPC) decoder in digital video broadcasting - second generation satellite (DVB-S2)

In recent years, LDPC codes are gaining a lot of attention among researchers. Its near-Shannon performance combined with its highly parallel architecture and lesser complexity compared to Turbo-codes has made LDPC codes one of the most popular forward error correction (FEC) codes in most of the recently ratified wireless communication standards. This thesis focuses on one of these standards, namely the DVB-S2 standard that was ratified in 2005. In this thesis, the design and architecture of a FPGA implementation of an LDPC decoder for the DVB-S2 standard are presented. The decoder architecture is an improvement over others that are published in the current literature. Novel algorithms are devised to use a memory mapping scheme that allows for 360 functional units (FUs) used in decoding to be implemented using the Sum-Product Algorithm (SPA). The functional units (FU) are optimized for reduced hardware resource utilization on a FPGA with a large number of configurable logic blocks (CLBs) and memory blocks. A novel design of a parity-check module (PCM) is presented that verifies the parity-check equations of the LDPC codes. Furthermore, a special characteristic of five of the codes defined in the DVB-S2 standard and their influence on the decoder design is discussed. Three versions of the LDPC decoder are implemented, namely the 360-FU decoder, the 180-FU decoder and the hybrid 360/180-FU decoder. The decoders are synthesized for two FPGAs. A Xilinx Virtex-II Pro family FPGA is used for comparison purposes and a Xilinx Virtex-6 family FPGA is used to demonstrate the portability of the design. The synthesis results show that the hardware resource utilization and minimum throughput of the decoders presented are competitive with a DVB-S2 LDPC decoder found in the current literature that also uses FPGA technology

Low-Power Embedded Design Solutions and Low-Latency On-Chip Interconnect Architecture for System-On-Chip Design

This dissertation presents three design solutions to support several key system-on-chip (SoC) issues to achieve low-power and high performance. These are: 1) joint source and channel decoding (JSCD) schemes for low-power SoCs used in portable multimedia systems, 2) efficient on-chip interconnect architecture for massive multimedia data streaming on multiprocessor SoCs (MPSoCs), and 3) data processing architecture for low-power SoCs in distributed sensor network (DSS) systems and its implementation. The first part includes a low-power embedded low density parity check code (LDPC) - H.264 joint decoding architecture to lower the baseband energy consumption of a channel decoder using joint source decoding and dynamic voltage and frequency scaling (DVFS). A low-power multiple-input multiple-output (MIMO) and H.264 video joint detector/decoder design that minimizes energy for portable, wireless embedded systems is also designed. In the second part, a link-level quality of service (QoS) scheme using unequal error protection (UEP) for low-power network-on-chip (NoC) and low latency on-chip network designs for MPSoCs is proposed. This part contains WaveSync, a low-latency focused network-on-chip architecture for globally-asynchronous locally-synchronous (GALS) designs and a simultaneous dual-path routing (SDPR) scheme utilizing path diversity present in typical mesh topology network-on-chips. SDPR is akin to having a higher link width but without the significant hardware overhead associated with simple bus width scaling. The last part shows data processing unit designs for embedded SoCs. We propose a data processing and control logic design for a new radiation detection sensor system generating data at or above Peta-bits-per-second level. Implementation results show that the intended clock rate is achieved within the power target of less than 200mW. We also present a digital signal processing (DSP) accelerator supporting configurable MAC, FFT, FIR, and 3-D cross product operations for embedded SoCs. It consumes 12.35mW along with 0.167mm2 area at 333MHz