Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 µm CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator

Digitally Interfaced Analog Correlation Filter System for Object Tracking Applications

Advanced correlation filters have been employed in a wide variety of image processing and pattern recognition applications such as automatic target recognition and biometric recognition. Among those, object recognition and tracking have received more attention recently due to their wide range of applications such as autonomous cars, automated surveillance, human-computer interaction, and vehicle navigation.Although digital signal processing has long been used to realize such computational systems, they consume extensive silicon area and power. In fact, computational tasks that require low to moderate signal-to-noise ratios are more efficiently realized in analog than digital. However, analog signal processing has its own caveats. Mainly, noise and offset accumulation which degrades the accuracy, and lack of a scalable and standard input/output interface capable of managing a large number of analog data.Two digitally-interfaced analog correlation filter systems are proposed. While digital interfacing provided a standard and scalable way of communication with pre- and post-processing blocks without undermining the energy efficiency of the system, the multiply-accumulate operations were performed in analog. Moreover, non-volatile floating-gate memories are utilized as storage for coefficients. The proposed systems incorporate techniques to reduce the effects of analog circuit imperfections.The first system implements a 24x57 Gilbert-multiplier-based correlation filter. The I/O interface is implemented with low-power D/A and A/D converters and a correlated double sampling technique is implemented to reduce offset and lowfrequency noise at the output of analog array. The prototype chip occupies an area of 3.23mm2 and demonstrates a 25.2pJ/MAC energy-efficiency at 11.3 kVec/s and 3.2% RMSE.The second system realizes a 24x41 PWM-based correlation filter. Benefiting from a time-domain approach to multiplication, this system eliminates the need for explicit D/A and A/D converters. Careful utilization of clock and available hardware resources in the digital I/O interface, along with application of power management techniques has significantly reduced the circuit complexity and energy consumption of the system. Additionally, programmable transconductance amplifiers are incorporated at the output of the analog array for offset and gain error calibration. The prototype system occupies an area of 0.98mm2 and is expected to achieve an outstanding energy-efficiency of 3.6pJ/MAC at 319kVec/s with 0.28% RMSE

Low power CMOS analog multipliers.

CMOS analog multiplier is a very important building block and programming element in analog signal processing. Although high-performance multipliers using bipolar transistors have been available for 40 years, CMOS multiplier implementation is still a challenging subject especially for low-power and low-noise circuit design. Since the supply voltage is normally fixed for analog multiplier structures, we use the total current to represent the power dissipation. Our basic idea for low power design of analog multipliers is to fit most of the transistors into the linear region, while at the same time keeping the drain-to-source voltage as low as possible to decease the drain current. And also, we use PMOS transistors for the devices working in the saturation region to further decrease the drain current and improve the linearity performance. Two low power CMOS analog multiplier designs have been proposed in this thesis. We gave detailed performance analysis and some design considerations for these structures. Cadence Hspice simulation verified our analysis. To ensure a fair comparison, we also simulated the performance of a previous multiplier structure, which was considered to be one of the best multiplier structures with low power and low noise performance. Extensive experiments and comparison for these structures show that the proposed CMOS analog multipliers have much less power dissipation than that of previous structures, while at the same time, satisfying other performance requirements. The proposed analog multipliers would be good choices in the applications where low power dissipation is an important consideration.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .L5. Source: Masters Abstracts International, Volume: 43-01, page: 0280. Adviser: Chunhong Chen. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

High Temperature Silicon Carbide Mixed-signal Circuits for Integrated Control and Data Acquisition

Wide bandgap semiconductor materials such as gallium nitride (GaN) and silicon carbide have grown in popularity as a substrate for power devices for high temperature and high voltage applications over the last two decades. Recent research has been focused on the design of integrated circuits for protection and control in these wide bandgap materials. The ICs developed in SiC and GaN can not only complement the power devices in high voltage and high frequency applications, but can also be used for standalone high temperature control and data acquisition circuitry. This dissertation work aims to explore the possibilities in high temperature and wide bandgap circuit design by developing a host of mixed-signal circuits that can be used for control and data acquisition. These include a family of current-mode signal processing circuits, general purpose amplifiers and comparators, and 8-bit data converters. The signal processing circuits along with amplifiers and comparators are then used to develop an integrated mixed-signal controller for a DC-DC flyback converter in a microinverter application. The 8-bit SAR ADC and the 8-bit R-2R ladder DAC open up the possibility of a remote data acquisition and control system in high temperature environments. The circuits and systems presented here offer a gateway to great opportunities in high temperature and power electronics ICs in SiC

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Microelectronic cmos implementation of a machine learning technique for sensor calibration

An integrated machine-learning based adaptive circuit for sensor calibration implemented in standard 0.18μm CMOS technology with 1.8V power supply is presented in this paper. In addition to linearizing the device response, the proposed system is also capable to correct offset and gain errors. The building blocks conforming the adaptive system are designed and experimentally characterized to generate numerical high-level models which are used to verify the proper performance of each analog block within a defined multilayer perceptron architecture. The network weights, obtained from the learning phase, are stored in a microcontroller EEPROM memory, and then loaded into each of the registers of the proposed integrated prototype. In order to verify the proposed system performance, the non-linear characteristic of a thermistor is compensated as an application example, achieving a relative error er below 3% within an input span of 130°C, which is almost 6 times less than the uncorrected response. The power consumption of the whole system is 1.4mW and it has an active area of 0.86mm 2 . The digital programmability of the network weights provides flexibility when a sensor change is required

Design Of A Current Conveyor Analogue Multiplier For Energy Meter Using 0.35 Μm Mimos Cmos Technology

Analogue VLSI circuits are essential in many real-time signal processing applications as naturally occurring signals are analogue. The four-quadrant analogue multiplier is a key building block in analogue signal processing circuits. It is used to construct circuits like the modulator and waveform generator. The ideal output (Vout) of a multiplier is related to the inputs by Vout = KmVXVY, where Km is the multiplier gain with units of V-1, and VX and VY are input voltages. In reality, imperfections exist in the multiplier gain, resulting in offsets and nonlinearities. Important parameters such as power dissipation, supply voltage, input dynamic range, bandwidth, total harmonic distortion (THD) and linearity are used to assess the performance of an analogue multiplier. Nowadays both digital and analogue systems are routinely integrated onto single chips. Digital circuits commonly use low-voltage supply and employ techniques to reduce power consumption. Mixed analogue-digital circuits must be designed to operate in a low-voltage, low-power environment. Conventional analogue multipliers designed with low supply voltage suffer from performance trade-offs, resulting in low bandwidth and low dynamic range because the design of analogue circuits is a trade-off of various performance parameters such as power dissipation, supply voltage, gain, linearity and noise. The objective of this research is to design a low-voltage, low-power CMOS analogue multiplier that will address the above problems. The multiplier is designed in a modified bridged-triode scheme (MBTS) and uses current conveyors. As all analogue circuits can be decomposed into several sub-circuits, the performance of these sub-circuits decides the characteristics of the resultant circuit structure. The proposed circuit makes use of the current conveyor’s many special features, such as high output impedance and large bandwidth, to construct a low-voltage fourquadrant multiplier. The analogue multiplier designed in this research operates with a supply voltage of ±1V. The total harmonic distortion obtained from this multiplier is less than two percent, the input operating swing is up to 1Vpp, and the bandwidth achieved is more than 100MHz. It is designed using a 0.35μm technology from the Malaysian Institute of Microelectronics (MIMOS). In addition, an RMS-to-DC converter is designed using the same low-voltage design technique used for designing the adaptively-biased low-voltage current mirror (ABLVCM). Then an energy meter is designed using this analogue multiplier and the RMS-to-DC converter